Modeling and optimization of hierarchical synchronous circuits

Proceedings of the 1995 European Conference on Design and Test, EDTC 1995

Volumn , Issue , 1995, Pages 144-149

  Lin, Bill ^a   De Jong, Gjalt ^a   Kolks, Tilman ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

TIMING CIRCUITS;

GENERAL METHOD; INDIVIDUAL COMPONENTS; MODELING AND OPTIMIZATION; SET MODELING; STATE MACHINE; SUBSTITUTION PROBLEM; SYNCHRONOUS CIRCUITS; SYNCHRONOUS DESIGNS;

DEGREES OF FREEDOM (MECHANICS);

EID: 85011667710     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/edtc.1995.470406     Document Type: Conference Paper

References (12)

1. R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation", IEEE Trans, on Computers, vol. 35, no. 8, Aug. 1986, pp. 677-691.
2. J. R. Burch, D. Dill, E. Wolf, and G. De Micheli, "Modeling Hierarchical Combinational Circuits", Proc. ICCAD, Nov. 1993.
3. O. Coudert, C. Berthet, and J.C. Madre, "Verification of Sequential Machines Using Boolean Functional Vectors", IMEC- IFIP Int. Workshop on Applied Formal Methods for Correct VLSI Design, ed. L. Claesen, Houthalen, Belgium, Nov. 1989, pp. 111-128.
4. M. Damiani, "Nondeterministic Finite-State Machines and Sequential Don't Cares", European Design and Test Conference, Paris, Feb. 1994, pp. 192-198.
5. S. Devadas, "Optimizing Interacting Finite State Machines Using Sequential Don't Cares", IEEE Trans, on CAD, vol. 10, no. 12, Dec. 1991, pp. 1473-1484.
6. D.L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits, ACM Distinguished Dissertations, MIT Press, Cambridge, MA, 1989.
7. J. Kim and M.M. Newborn, "The Simplification of Sequential Machines with Input Restrictions", IEEE Trans, on Computers, vol. 21, Dec. 1972, pp. 1440-1443.
8. J.K. Rho, G. Hachtel, and F. Somenzi, "Don't Care Sequences and the Optimization of Interacting Finite State Machines", Proc. ICCAD, Nov. 1991.
9. E.M. Sentovich, K.J. Singh, C. Moon, H. Savoj, R.K. Brayton, and A. Sangiovanni-Vincentelli, "Sequential Circuit Design Using Synthesis and Optimization", Proc. ICCD, Oct. 1992.
10. H. Touati, H. Savoj, B. Lin, R.K. Brayton, and A. Sangiovanni-Vincentelli, "Implicit State Enumeration of Finite State Machines Using BDD's", Proc. ICCAD, Nov. 1990.
11. J.L.A. van de Snepscheut. Trace Theory and VLSI Design, Lecture Notes in Computer Science 200, Springer Verlag, Berlin, 1985.
12. Y. Watanabe and R.K. Brayton, "The Maximum Set of Permissible Behaviors for FSM Networks", Proc. ICCAD, Nov. 1993, pp. 316-320.