Exploiting the temporal logic hierarchy and the non-confluence property for efficient LTL synthesis

Electronic Proceedings in Theoretical Computer Science, EPTCS

Volumn 25, Issue , 2010, Pages 89-102

  Morgenstern, Andreas ^a   Schneider, Klaus ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY; COMPUTER CIRCUITS; FORMAL VERIFICATION;

CONFLUENCE PROPERTY; DETERMINIZATION; LINEAR TEMPORAL LOGIC SPECIFICATIONS; LOGIC HIERARCHY; LTL FORMULAE; REACTIVE SYSTEM; SYNTHESIS PROCEDURE; WINNING STRATEGY;

TEMPORAL LOGIC;

EID: 85009892138     PISSN: 20752180     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.4204/EPTCS.25.11     Document Type: Conference Paper

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