Application of via post interconnection for build up printed circuit board

2nd 1998 IEMT/IMC Symposium

Volumn 1998-April, Issue , 1998, Pages 312-315

  Kobayashi, T ^a   Itaya, S ^b   Ikeda, K ^c   Kawasaki, J ^a   Honma, H ^a  

^a KANTO GAKUIN UNIVERSITY   (Japan)

^b OKI ELECTRIC INDUSTRY CO   (Japan)

^c Oki Printed Circuits Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTRIC NETWORK PARAMETERS; ELECTROLESS PLATING; ELECTROPLATING; METALLIZING; MICROELECTRONICS; MINIATURE INSTRUMENTS; OXIDE FILMS; TIMING CIRCUITS;

CU ELECTROPLATING; ELECTRICAL RELIABILITY; ELECTROLESS PLATING PROCESS; ELECTRONIC COMPONENT; PRETREATMENT PROCESS; PRINTED CIRCUIT BOARD (PCBS); PRODUCTION TECHNIQUES; UNDERLAYERS;

PRINTED CIRCUIT BOARDS;

EID: 85009623439     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMTIM.1998.704666     Document Type: Conference Paper

References (3)

1. S. Itaya, et al. :Proc. 7th MES, p. 157, 1997.
2. Knakakulki, et al.. :Proc. 9th JIPC Annual Meeting, 35, 1995.
3. S. Itaya, et al. :Proc. IEEEICPMT symposium, p. 96, 1995.