A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 1, 2008, Pages 132-140

  Villa, Corrado ^a   Vimercati, Daniele ^a   Schippers, Stefan ^a   Polizzi, Salvatore ^a   Scavuzzo, Andrea ^a   Perroni, Maurizio ^a   Gaibotti, Maurizio ^a   Luigi Sali, Mauro ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

DDR interface; multilevel flash; NOR flash memory

Indexed keywords

EID: 85008040429     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.2008.916028     Document Type: Article

References (6)

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6. C. Villa et al., “A 125 MHz burst-mode flexible read-while-write 256 Mbit 2 b/c 1.8 V NOR flash memory,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 52–53.