Adaptive circuits using pFET floating-gate devices

Proceedings - 20th Anniversary Conference on Advanced Research in VLSI, ARVLSI 1999

Volumn , Issue , 1999, Pages 215-219

  Hasler, Paul ^a   Minch, Bradley A ^b   Diorio, Chris ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Department of Obstetrics Gynecology   (United States)

^c UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL RESEARCH; CONTINUOUS TIME SYSTEMS; ELECTRON INJECTION; ELECTRON TUNNELING; FIELD EFFECT TRANSISTORS; HOT ELECTRONS; LOGIC GATES; TIMING CIRCUITS; VLSI CIRCUITS; VOLTAGE DIVIDERS;

ADAPTATION AND LEARNING; CO-OPERATIVE BEHAVIORS; CONTINUOUS-TIME CIRCUITS; DOUBLE-POLY CMOS TECHNOLOGY; FLOATING GATE CIRCUITS; FLOATING GATE TECHNOLOGY; FLOATING-GATE DEVICES; TRANSLINEAR CIRCUITS;

MOS DEVICES;

EID: 85006017281     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.1999.756050     Document Type: Conference Paper

References (27)

1. D. Kahng and S. M. Sze, "A oating-gate and its application to memory devices, " The Bell System Technical Journal, vol. 46, no. 4, 1967, pp. 1288-1295.
2. ISD Data Book: Voice Recording and Playback ICs, ISD, San Jose, 1996, 2nd edition.
3. P. Hasler, C. Diorio, B. A. Minch, and C. Mead, "Single Transistor Learning Synapses, " Advances in Neural Information Processing Systems 7, MIT Press, 1995, pp. 817-824. Also at http://users. ece. gatech. edu/-phasler.
4. P. Hasler, B. A. Minch, C. Diorio, and C. Mead, "An autozeroing amplifier using pFET hot-electron injection, " Proceedings of the International Symposium on Circuits and Systems, At-lanta, vol. 3, 1996, pp. 325-328. Also at http://users. ece. gatech. edu/-phasler.
5. P. Hasler, B. A. Minch, C. Diorio, and C. A. Mead, "An autozeroing oating-gate amplifier, " Accepted for publication in Circuits and Systems II: Digital and Analog Signal Processing Also will be at http://users. ece. gatech. edu/-phasler.
6. P. Hasler, A. Andreou, C. Diorio, B. A. Minch, and C. A. Mead, "Impact ionization and hot-electron injection derived consistently from Boltzmann transport, " VLSI Design, in Press.
7. P. Hasler, C. Diorio, and B. A. Minch, "A four-quadrant oating-gate synapse, " Proceed-ings of IEEE International Symposium on Circuits and Systems, Monterey, 1998. Also at http://users. ece. gatech. edu/-phasler.
8. P. Hasler, Foundations of Learning in Analog VLSI, California Institute of Technology, Febru-ary 1997. Also at http://users. ece. gatech. edu/-phasler.
9. P. Hasler, T. Stanford, B. A. Minch, and C. Diorio, "An Autozeroing Floating-Gate Second-Order Section, " Proceedings of IEEE International Symposium on Circuits and Systems, Mon-terey, 1998. Also at http://users. ece. gatech. edu/-phasler.
10. B. A. Minch, C. Diorio, P. Hasler, and C. A. Mead, "Translinear circuits using subthreshold oating-gate MOS transistors, " Analog Integrated Circuits and Signal Processing, vol. 9, no. 2, 1996, pp 167-179. Also at http://users. ece. gatech. edu/-phasler.
11. B. A. Minch, C. Diorio, P. Hasler, and C. A. Mead, "The matching of small capacitors for analog VLSI, " Proceedings of the International Symposium on Circuits and Systems, Atlanta, vol. 1, 1996, pp. 238-241. Also at http://users. ece. gatech. edu/-phasler.
12. R. R. Harison, P. Hasler, and B. A. Minch, "Floating-gate CMOS analog memory cell array, " Proceedings of IEEE International Symposium on Circuits and Systems, Monterey, 1998. Also at http://users. ece. gatech. edu/-phasler.
13. A. Apsel, T. Stanford, and P. Hasler, "An adaptive oating-gate olfaction sensor, " Proceed-ings of IEEE International Symposium on Circuits and Systems, Monterey, 1998. Also at http://users. ece. gatech. edu/-phasler.
14. C. Diorio, P. Hasler, B. A. Minch, and C. Mead, "A complementary pair of four-terminal silicon synapses, " Analog Integrated Circuits and Signal Processing, 1997.
15. C. Diorio, S. Mahajan, P. Hasler, B. A. Minch, and C. Mead, "A high resolution non-volatile analog memory cell, " Proceedings of the International Conference of Circuits and Systems, Seattle, 1995, pp. 2233-2236.
16. A. Thomsen and M. A. Brooke, "A oating gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process, " IEEE Electron Device Letters, vol. 12, 1991, pp. 111-113.
17. T. Shibata and T. Ohmi, "A functional MOS transistor featuring gate-level weighted sum and threshold operations, " IEEE Transactions on Electron Devices, vol. 39, no. 6, 1992, pp. 1444-1455.
18. R. G. Benson and D. A. Kerns, "UV-activated conductances allow for multiple time-scale learn-ing, " IEEE Transactions on Neural Networks, vol. 4, no. 3, 1993, pp. 434-440.
19. K. Yang and A. G. Andreou, "A Multiple Input Difierential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET, " Journal of Analog Integrated Circuits and Signal Processing, vol. 6, no. 3, 1994, pp 197-208.
20. H. V. Tran, T. Blyth, D. Sowards, L. Engh, B. S. Nataraj, T. Dunne, H. Wong, V. Serin, T. Lam, H. Hazarian, and G. Hu, "A 2. 5V 256-level non-volatile analog storage device using EEPROM technology, " Proceedings of IEEE International Solid-State Circuits Conference, 1996, pp. 270-271.
21. J. Ramirez-Angulo, "+-0. 75V BiCMOS Four Quadrant Analog Multiplier with Rail-Rail Input Signal-Swing, " in Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, Atlanta, GA, vol. 1, 1996, pp. 242-245.
22. Y. Berger, D. T. Wisland, T. S. Lande, and S. Mikkelsen, "Ultra low-voltage digital oating-gate UVMOS Circuits, " Proceedings of IEEE International Symposium on Circuits and Systems, Monterey, 1998.
23. C. A. Mead, Analog VLSI and Neural Systems, Addison-Wesley, Reading, MA, 1989.
24. M. Lenzlinger and E. H. Snow, "Fowler-Nordheim tunneling into thermally grown Si02, " Jour-nal of Applied Physics, vol. 40, no. 1, 1969, pp. 278-283.
25. C. A. Mead, "Scaling of MOS technology to submicrometer feature sizes, " Journal of VLSI Signal Processing, vol. 8, 1994, pp. 9-25.
26. Y. Xu, Electron Transport through Thin Film Amorphous Silicon | A Tunneling Study, Ph. D. dissertation, Stanford University, 1992.
27. T. A. Fjeldly and M. Shur, "Threshold voltage modeling and the subthreshold regime of op-eration of short-channel MOSFETs, " IEEE Transactions on Electron Devices, vol. 40, no. 1, 1993, pp. 137-145.