A survey on performance of on-chip cache for multi-core architectures

ACM International Conference Proceeding Series

Volumn 25-26-August-2016, Issue , 2016, Pages

  Krishna Priya, B ^a   Joshi, Amit D ^a   Ramasubramanian, N ^a  

^a NATIONAL INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Energy consumption; Improvement techniques; On chip cache; Performance; Size of processor

Indexed keywords

CACHE MEMORY; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; ENERGY UTILIZATION; INFORMATION SCIENCE; SURVEYS;

ENERGY-EFFICIENT TECHNIQUES; IMPROVEMENT TECHNIQUE; INSTRUCTION PER CYCLES; MULTICORE ARCHITECTURES; ON-CHIP CACHE; PERFORMANCE; PERFORMANCE ENHANCEMENTS; SIZE OF PROCESSOR;

COMPUTER ARCHITECTURE;

EID: 84997235991     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2980258.2980336     Document Type: Conference Paper

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