Fast SUBMAP decoders for duo-binary turbo-codes

ICCSC 2002 - 1st IEEE International Conference on Circuits and Systems for Communications, Proceedings

Volumn 2002-June, Issue , 2002, Pages 150-153

  Saouter, Y ^a   Berrou, C ^a  

^a NONE

Author keywords

Gigabit networking; SUBMAP; Turbo codes; VLSI

Indexed keywords

BINS; CODES (SYMBOLS); DECODING; ERROR CORRECTION; RECONFIGURABLE HARDWARE;

COMMUNICATIONS SYSTEMS; DATA FRAMES; DECODING ALGORITHM; GIGABIT NETWORKING; MAXIMUM A POSTERIORI ALGORITHM; NOISY CHANNEL; SUBMAP; VLSI;

TURBO CODES;

EID: 84991011122     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OCCSC.2002.1029067     Document Type: Conference Paper

References (11)

1. C. Berrou and A. Glavieux. Near Shannon limit error correcting coding and decoding: Turbo-codes. In Intl. Conf. on Comm., vol. 2, pp. 1064-1070, Geneva, Switzerland, 1993.
2. B. Vucetic and J. Yuan. Turbo Codes - Principles and Applications. Kluwer Academics Publishers, 2000.
3. C. Berrou and M. Jezequel. Non-binary convolutional codes for turbo coding. Electr. Let., 35(1):39, Jan. 1999.
4. C. Bettstetter. Turbo decoding with tail-biting trellises. Diplomarbeit, July 1998.
5. C. Douillard, M. Jezequel, C. Berrou, N. Brengarth, J. Tousch, and N. Pham. The Turbo Code Standard for DVB-RCS. In 2nd Intl. Symp. on Turbo Codes & Related Topics, pp. 535-538, Brest, France, Sept. 2000.
6. P. Robertson, P. Hoeher, and E. Villebrun. Optimal and Suboptimal Maximum a Posteriori Algorithms suitable for Turbo Decoding. Euro. Tr. Telecomm., 8:119-125, Mar.-Apr. 1997.
7. L.R. Bahl, J. Cocke, F. Jelinek, and J. Raviv. Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate. IEEE Tr. Inf. Th., IT-20:284-287, Mar. 1974.
8. A. Dingninou, F. Raouafi, and C. Berrou. Organisation de la mémoire dans un turbo décodeur utilisant l'algorithme SUBMAP. In GRETSI'99, pp. 71-74, Vannes, France, Sept. 1999.
9. A.J. Viterbi. An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes. IEEE J. on Sel. Areas in Comm., SAC-16(2):260-264, Feb. 1998.
10. R.P. Brent and H.T. Kung. A Regular Layout for Parallel Adders. IEEE Tr. Comp., C-31:260-264, Mar. 1982.
11. C.Y. Chow and J.E. Robertson. Logical Design of a Redundant Binary Adder. In Proc. of the 4th Symp. on Comp. Arith., pp. 109-115, Oct. 1978.