A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2016-September, Issue , 2016, Pages

  Nam, Jae Won ^a   Hassanpourghadi, Mohsen ^a   Zhang, Aoyang ^a   Chen, Mike Shuo Wei ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

ADC; CMOS; high speed; SAR; time interleave

Indexed keywords

INTERPOLATION; RECONFIGURABLE HARDWARE; VLSI CIRCUITS;

CONVERSION CYCLES; HIGH SPEED; INPUT FREQUENCY; INTERPOLATION TECHNIQUES; LOW-POWER CONSUMPTION; POWER EFFICIENCY; TIME INTERLEAVE; TIME-INTERLEAVING;

CMOS INTEGRATED CIRCUITS;

EID: 84990929658     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2016.7573516     Document Type: Conference Paper

References (3)

1. H.-K. Hong et al., ISSCC, 2015.
2. C.-H. Chan et al., ISSCC, 2015.
3. B. Murmann, "ADC Performance Survey 1997-2015," [Online].