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Bell System Technical Journal
Volumn 52, Issue 1, 1973, Pages 135-142
A Proper Model for Testing the Planarity of Electrical Circuits

(2)  Goldstein, A J a   Schweikert, D G a  

a NONE
Author keywords

[No Author keywords available]
Indexed keywords

EID: 84990479665     PISSN: 00058580     EISSN: 15387305     Source Type: Journal    
DOI: 10.1002/j.1538-7305.1973.tb03188.x     Document Type: Article
Times cited : (2)
References (8)
  • 2
    • 84990437332 scopus 로고
    • “An Efficient and Constructive Algorithm for Testing Whether a Graph Can Be Embedded in the Plane”, Proc. Conf. on Combinatorics and Graphs, Princeton
    • (1963)
    • Goldstein, A.J.1
  • 3
    • 33745159104 scopus 로고
    • “Computer Recognition and Extraction of Planar Graphs from the Incidence Matrix”, IEEE Trans. Circ. Theory, IS
    • (1966) , pp. 154-163
    • Fisher, G.J.1    Wing, O.2
  • 4
    • 84990448645 scopus 로고
    • “Planarity Testing in V Log V Steps”, Proc. of IFIP Congress, Ljubljana, Yugoslavia, Booklet TA2, pp.
    • (1971) , pp. 18-22
    • Hopcroft, J.1    Tarjan, R.2
  • 5
    • 84990487962 scopus 로고
    • “An Efficient Planarity Algorithm”, Stanford University Report STAN‐CS‐244‐71
    • (1971)
    • Tarjan, R.1
  • 6
    • 84990487959 scopus 로고    scopus 로고
    • “Topological Synthesis Procedure for Circuit Integration”, Proc. 1969 IEEE Int. Solid‐State Circ. Conf., pp.
    • Engl, W.L.1    Mylnski, D.A.2
  • 7
    • 84990456273 scopus 로고
    • “A Proper Model for the Partitioning of Electrical Circuits”, Proc. 9th Design Automation Workshop, Dallas
    • (1971) , pp. 57-62
    • Schweikert, D.G.1    Kernighan, B.W.2
  • 8
    • 0015141551 scopus 로고
    • “Printed‐Wiring‐Board Layout by Computer”, Electronics and Power
    • (1971) , pp. 376-379
    • Rose, N.A.1    Oldfield, J.V.2

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.