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Volumn , Issue , 1993, Pages 74-83
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Locking effects in multiprocessor implementations of protocols
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Author keywords
[No Author keywords available]
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Indexed keywords
INTERNET PROTOCOLS;
LOCKS (FASTENERS);
MEMORY ARCHITECTURE;
MULTIPROCESSING SYSTEMS;
PARALLEL PROCESSING SYSTEMS;
TRANSMISSION CONTROL PROTOCOL;
LOCKING EFFECTS;
MUTUAL EXCLUSIONS;
PARALLEL IMPLEMENTATIONS;
PERFORMANCE PREDICTION;
PROTOCOL PROCESSING;
PROTOCOL STATE;
SHARED MEMORY MULTIPROCESSOR;
UNIVERSITY OF ARIZONA;
NETWORK ARCHITECTURE;
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EID: 84989842064
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/166237.166245 Document Type: Conference Paper |
Times cited : (40)
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References (11)
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