A "greedy" channel router

Proceedings - Design Automation Conference

Volumn , Issue , 1982, Pages 418-424

  Rivest, Rouald L ^a   Fiduccia, Charles M ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b GE GLOBAL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; DESIGN;

CHANNEL DENSITY; CHANNEL ROUTERS; SINGLE-TRACKS;

COMPUTER AIDED DESIGN;

EID: 84989496148     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1982.1585533     Document Type: Conference Paper

References (24)

1. Alford, S. "DYCHAR: A Channel Router which uses dynamic channel assignment," MIT Bachelor's thesis. (May 1980).
2. Asano, T., T. Kitahashi, and K. Tauaka, "On a Method of Realizing Minimum-Width Wiring," Electronics and Communications in Japan, Vol. J59-A, No. 2 (1976), 29-39.
3. Brown, D. and R. L. Rivest, "New Lower Bounds on Channel Width", Proc. CMU Conference on VLSI Systems and Computations, (Computer Science Press 1981) 178-185.
4. Deutsch, D. N., "A 'Dogleg' Channel Router," Proc. 13-th Design Automation Conference, IEEE (1976), 425-433.
5. Dolev, D, K. Karplus, A. Siegel, A. Strong, and J. Ullman, "Optimal Wiring Between Rectangles," Proc. 13th Annual ACM Symposium on Theory of Computing (May 1981), 312-317.
6. Garey, M. and D. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, (Freeman, 1979).
7. Hashimoto, A. and J. Stevens, "Wire Routing by Optimizing Channel Assignment within Large Apertures," Proc. 8-th Design Automation Workshop, IEEE (1971), 214-224.
8. Hightower, D., "The Interconnection Problem: A Tutorial," Computer 7, 4 (April 1974), 18-32.
9. Kawamoto, T. and Y. Kajitani, "The Minimum Width Routing of of a 2-Row 2-Layer Polycell-Layout," Proc. 16th Design Automation Conference, IEEE (1979), 290-296.
10. Kernighan, B., D. Schweikert, and G. Persky. "An Optimal Channel-Routing Algorithm for Polycell Layouts of Integrated Circuits," Proc. 10-th Design Automation Workshop, IEEE (1973), 50-59.
11. Koschella, J., "A Placement/Interconnect Channel Router: Cutting your PI into Slices," Bachelor's Thesis. MIT Department of Electrical Engineering and Computer Science. (May 1981).
12. LaPaugh, A., "Algorithms for Integrated Circuit Layout: an Analytic Approach," Ph.D. Thesis, MIT Laboratory for Computer Science Report TR-248 (November 1980).
13. Leighton, T., "New Lower Bounds for Channel Routing," To appear.
14. Leiserson, C, and R. Pinter, "Optimal Placement for River Routing," Proc. CMU Conference on VLSI Systems and Computations, (Computer Science Press 1981), 126-143.
15. Persky, C, D. Deutsch, and D. Schweikert, "LTX - A Minicomputer-Based System for Automated LSI Layout," Journal of Design Automation and Fault-Tolerant Computing 1, 3 (May 1977), 217-255.
16. Pinter, R., "Optimal Routing in Rectilinear Channels," Proc. CMU Conference on VLSI Systems and Computations, (Computer Science Press 1981), 160-177.
17. Rivcst, R. L., "'Benchmark' Channel-Routing Problems," in preparation.
18. Rivest, R. L., "The 'PI' (Placement and Interconnect) System". Proc. 10th Design Automation Conference, (Las Vegas, 1982)
19. Rivest, R. L., A. E. Baratz, and G. Miller, "Provably Good Channel-Routing Algorithms," Proc. CMU Conference on VLSI Systems and Computations, (Computer Science Press 1981), 153-159.
20. Sahni, S. and A. Bhatt, "The Complexity of Design Automation Problems," Proc. 17th Design Automation Conference, IEEE (June 1980), 402-411.
21. Soukup, J., "Circuit Layout," Proc. of the IEEE, Vol. 69, No. 10(Oct. 1981), 1281-1304.
22. Szymanski, T., "Dogleg Channel Routing is NP-Complete," To appear.
23. Tompa, M., "An Optimal Solution to a Wire-Routing Problem," Proc. 12th Annual A CM Symposium on Theory of Computing, (April 1980), 201-210.
24. Yoshimura, T. and E. Kuh, "Efficient Algorithms for Channel Routing," U. C. Berkeley Electronics Research Laboratory Memo. No. M80/43 (August 1980).