3-D topography simulation of via holes using generalized solid modeling

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 173-176

  Tazawa, S ^a   Leon, F A ^a,b   Anderson, G D ^a,b   Abe, T ^a   Saito, K ^a   Yoshii, A ^a   Scharfetter, D L ^a,b  

^a NTT CORPORATION   (Japan)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION; ELECTRON DEVICES; ETCHING; TOPOGRAPHY;

3-D TOPOGRAPHY; 3D STRUCTURES; BOUNDARY REPRESENTATION MODELS; ETCHING RATE; LOCAL DEPOSITION; MOVEMENT VECTOR; PLANE MODEL; REMOVAL ALGORITHMS;

SIMULATORS;

EID: 84989437278     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307335     Document Type: Conference Paper

References (6)

1. W. E. Scheckler et al., Symp. VLSI Technol. Dig., p. 97, May 1991.
2. M. Fujinaga et al., IEEE Trans. Electron Devices, vol. ED-37, no. 10, p. 2183, Oct. 1990.
3. G. M. Koppelman et al., IBM J. Res. Dev. 27, p. 149, 1983.
4. M. Mantyla, "An introduction to solid modeling, " Computer Science Press, 1988.
5. S. Tazawa et al., Symp. VLSI Technol. Dig., p. 45, May 1989.
6. S. Tazawa et al., IEEE Trans. Semiconductor Manufacturing, vol. 5, no. 1, p. 27, Feb. 1992.