A 3.3 v high speed CMOS PLL with a two-stage self-feedback ring oscillator

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 287-290

  Moon, Yeon Kug ^a   Yoon, Kwang Sub ^a  

^a Inha University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84988763211     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824085     Document Type: Conference Paper

References (6)

1. Turgut S. Aytur and Behzad Razavi, "A 2-GHz, 6-mW BiCMOS Frequency Synthesizer, " IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1457-1462, Dec. 1995.
2. Joonbae Park, Wonchan Kim, "An Auto-Ranging 50-210Mb/s Clock Recovery Circuit with a Time-to-Digital Converter, " ISSCC Dig. Tech. Papers, pp. 350-351, Feb. 1999.
3. Ian A. Young, Jeffrey K. Greason, Keng L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors, " IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, Nov. 1992.
4. Ilya Novof, John Austin, Ram Kelkar, Don Strayer, Steve Wyatt, "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 ps Jitter, " ISSCC Dig. Tech. Papers, pp. 112-113, Feb. 1995.
5. Kamran Iravani and Gary Miller, "VCOs with Very Low Sensitivity to Noise on the Power Supply, " Proc. CICC pp. 24. 6. 1-24. 6. 4, 1998.
6. R. Jacob Baker, Harry W. Li, David E. Boyce, "CMOS Circuit Design, Layout, Simulation, " IEEE Press, 1998.