Semiconductor Manufacturing

Guide to State-of-the-Art Electron Devices

Volumn , Issue , 2013, Pages 121-132

  Singh, Rajendra ^a   Colombo, Luigi ^b   Schuegraf, Klaus ^c   Doering, Robert ^b   Diebold, Alain ^d  

^a CLEMSON UNIVERSITY   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c APPLIED MATERIALS INC   (United States)

^d STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

Defect Density; Etching; Evolution of Planar Process; Interconnect; Lithography; Packaging; Process Control; Silicon Wafer; Single wafer Processing; Yield

Indexed keywords

CHIP SCALE PACKAGES; DEFECT DENSITY; ETCHING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUITS; INTELLIGENT CONTROL; LITHOGRAPHY; PACKAGING; PROCESS CONTROL; SEMICONDUCTOR DEVICE MANUFACTURE; SINGLE CRYSTALS;

ADVANCED PROCESS CONTROL; INTERCONNECT; PLANAR PROCESS; SEMICONDUCTOR MANUFACTURING; SEMICONDUCTOR PRODUCTS; SINGLE WAFER PROCESSING; SINGLE-CRYSTAL SILICON WAFERS; YIELD;

SILICON WAFERS;

EID: 84986910371     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1002/9781118517543.ch10     Document Type: Chapter

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