A 16 b low-power-consumption digital signal processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1993, Pages 28-29

  Ueda, K ^a   Sugimura, T ^a   Okamoto, M ^a   Marui, S ^a   Ishikawa, T ^a   Sakakihara, M ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSORS; ELECTRIC POWER UTILIZATION;

BLOCK DIAGRAMS; CMOS PROCESSS; DIGITAL CELLULAR; DIGITAL SIGNAL PROCESSORS (DSP); DOUBLE METAL LAYERS; LOW-POWER CONSUMPTION; MULTIPLY ACCUMULATE; TRANSISTOR CIRCUIT;

DIGITAL SIGNAL PROCESSING;

EID: 84985777863     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1993.280098     Document Type: Conference Paper

References (2)

1. S unwoo, M. H., S. Park, K. Terry, "A Real-Time Implementationo f Key VSELP Routines on a 16-bit Chip", IEEE Dig. Tech. Pap. Int., Conf. Consumer Electronics, pp. 332-333, 1991.
2. Ueda, K., T. Sakao, T. Suzuki, 0. Nishijima, "A High Performance Digital Signal Processor VLSI : MN1900 Series", IEEE Proc. Int. Conf., Acoustics, Speech, and Signal Processing, pp. 21752178, 1986.