Modelling probabilistic cache representativeness in the presence of arbitrary access patterns

Proceedings - 2016 IEEE 19th International Symposium on Real-Time Distributed Computing, ISORC 2016

Volumn , Issue , 2016, Pages 142-149

  Milutinovic, Suzana ^a,b   Abella, Jaume ^a   Cazorla, Francisco J ^a,c  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c ARTIFICIAL INTELLIGENCE RESEARCH INSTITUTE IIIA CSIC   (Spain)

Author keywords

Probabilistic Timing Analysis; Real time; Safety; Verification; WCET

Indexed keywords

ACCIDENT PREVENTION; CACHE MEMORY; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; VERIFICATION;

CACHE SIMULATION; MEASUREMENT-BASED; REAL TIME; REAL-TIME EMBEDDED SYSTEMS; TIMING ANALYSIS; WCET; WORST CASE SCENARIO; WORST-CASE EXECUTION TIME;

REAL TIME SYSTEMS;

EID: 84983390755     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISORC.2016.28     Document Type: Conference Paper

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