Performance analyses and benchmarking for spintronic devices and interconnects

2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference, IITC/AMC 2016

Volumn , Issue , 2016, Pages 56-58

  Pan, Chenyun ^a   Chang, Sou Chi ^a   Naeemi, Azad ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

ASL; CSL; delay; energy delay product; Interconnect; mLogic; repeater; span of control; spintronic

Indexed keywords

BENCHMARKING; DOMAIN WALLS; LOGIC DEVICES; MAGNETOELECTRONICS; METALLIZING; PRODUCT DESIGN; SPIN HALL EFFECT; TELECOMMUNICATION REPEATERS;

DELAY; ENERGY DELAY PRODUCT; INTERCONNECT; MLOGIC; SPAN-OF-CONTROL;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84981335279     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC-AMC.2016.7507679     Document Type: Conference Paper

References (9)

1. K. J. Kuhn, "CMOS scaling for the 22nm node and beyond: Device physics and technology, " in VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on, 2011, pp. 1-2.
2. S. A. Wolf, J. Lu, et al, "The promise of nanomagnetics and spintronics for future logic and universal memory, " Proceedings of the IEEE, vol. 98, pp. 2155-2168, 2010.
3. D. Morris, D. Bromberg, et al, "mLogic: Ultra-low voltage non-volatile logic circuits using STT-MTJ devices, " in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 486-491.
4. S. Datta, S. Salahuddin, et al, "Non-volatile spin switch for Boolean and non-Boolean logic, " Applied Physics Letters, vol. 101, p. 252411, 2012.
5. B. Behin-Aein, D. Datta, et al, "Proposal for an all-spin logic device with built-in memory, " Nature nanotechnology, vol. 5, pp. 266-270, 2010.
6. D. E. Nikonov and I. A. Young, "Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits, " Exploratory Solid-State Computational Devices and Circuits, IEEE Journal on, vol. 1, pp. 3-11, 2015.
7. D. Matzke, "Will physical scalability sabotage performance gains, " Computer, pp. 37-39, 1997.
8. J. A. Davis, V. K. De, et al, "A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation, " Electron Devices, IEEE Transactions on, vol. 45, pp. 580-589, 1998.
9. M. C. Gaidis, E. Sullivan, et al, "Two-level BEOL processing for rapid iteration in MRAM development, " IBM journal of research and development, vol. 50, pp. 41-54, 2006