Architecture design for FPGA implementation of finite interval CMA

European Signal Processing Conference

Volumn 06-10-September-2004, Issue , 2015, Pages 2039-2042

  Hermanek, Antonin ^a,b   Schier, Jan ^b   Regalia, Phillip ^a  

^a INSTITUT NATIONAL DES TÉLÉCOMMUNICATIONS   (France)

^b INSTITUTE OF INFORMATION THEORY AND AUTOMATION   (Czech Republic)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; NUMBER THEORY; NUMBERING SYSTEMS;

ARCHITECTURE DESIGNS; CONSTANT MODULUS ALGORITHMS; FINITE INTERVALS; FLOATING-POINT CALCULATIONS; FPGA IMPLEMENTATIONS; LOGARITHMIC NUMBER SYSTEM; RESOURCE RE USE;

SIGNAL PROCESSING;

EID: 84979948883     PISSN: 22195491     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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5. P. A. Regalia. A finite interval constant modulus algorithm. In Proc. International Conference on Acoustics, Speech, and Signal Processing(ICASSP-2002), volume III, pages 2285-2288, Orlando, FL, May 13-17 2002.
6. P. A. Regalia and E. Kofidis. Monotonic convergence of fixed-point algorithms for ICA. IEEE Trans. Neural Networks, 14(4):943-949, July 2003.