Wear unleveling: Improving NAND flash lifetime by balancing page endurance

Proceedings of the 12th USENIX Conference on File and Storage Technologies, FAST 2014

Volumn , Issue , 2014, Pages 47-59

  Jimenez, Xavier ^a   Novo, David ^a   Ienne, Paolo ^a  

^a EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; NAND CIRCUITS; WEAR OF MATERIALS;

COMMERCIAL DEVICES; FLASH DEVICES; FLASH MEMORY CELL; FUTURE TECHNOLOGIES; LIFETIME EXTENSION; PROCESS VARIATION; PROGRAM/ERASE; STORAGE OVERHEAD;

FLASH MEMORY;

EID: 84979044620     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)

1. AUCLAIR, D., CRAIG, J., GUTERMAN, D., MANGAN, J., MEHROTRA, S., AND NORMAN, R. Soft errors handling in EEP-ROM devices, Aug. 12 1997. US Patent 5,657,332.
2. BATES, K., AND MCNUTT, B. OLTP application I/O, June 2007. http://traces.cs.umass.edu/index.php/Storage/Storage.
3. CAI, Y., HARATSCH, E., MUTLU, O., AND MAI, K. Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. In Design, Automation & Test in Europe Conf. & Exhibition (Dresden, Germany, Mar. 2012), pp. 521–26.
4. CHANG, L.-P. A hybrid approach to NAND-flash-based solid-state disks. IEEE Trans. Computers 59, 10 (Oct. 2010), 1337–49.
5. CHIAO, M.-L., AND CHANG, D.-W. ROSE: A novel flash translation layer for NAND flash memory based on hybrid address translation. IEEE Trans. Computers 60, 6 (June 2011), 753–66.
6. CHO, H., SHIN, D., AND EOM, Y. I. KAST: K-associative sector translation for NAND flash memory in real-time systems. In Design Automation and Test in Europe (Nice, France, Apr. 2009), pp. 507–12.
7. GRUPP, L. M., CAULFIELD, A. M., COBURN, J., SWANSON, S., YAAKOBI, E., SIEGEL, P. H., AND WOLF, J. K. Characterizing flash memory: Anomalies, observations, and applications. In ACM/IEEE Int. Symp. Microarchitecture (New York, NY, USA, Dec. 2009), pp. 24–33.
8. HETZLER, S. R. Flash endurance and retention monitoring. In Flash Memory Summit (Santa Clara, CA, USA, Aug. 2013).
9. IM, S., AND SHIN, D. ComboFTL: Improving performance and lifespan of MLC flash memory using SLC flash buffer. Journal of Systems Architecture 56, 12 (Dec. 2010), 641–53.
10. JIMENEZ, X., NOVO, D., AND IENNE, P. Software controlled cell bit-density to improve NAND flash lifetime. In Design Automation Conf. (San Francisco, California, USA, June 2012), pp. 229–34.
11. JIMENEZ, X., NOVO, D., AND IENNE, P. Phœnix: Reviving MLC blocks as SLC to extend NAND flash devices lifetime. In Design, Automation & Test in Europe Conf. & Exhibition (Grenoble, France, Mar. 2013), pp. 226–29.
12. LEE, S., SHIN, D., KIM, Y.-J., AND KIM, J. LAST: Locality-aware sector translation for NAND flash memory-based storage systems. ACM SIGOPS Operating Systems Review 42, 6 (Oct. 2008), 36–42.
13. LEE, S.-W., PARK, D.-J., CHUNG, T.-S., LEE, D.-H., PARK, S., AND SONG, H.-J. A log buffer-based flash translation layer using fully-associative sector translation. ACM Trans. Embedded Computing Systems 6, 3 (July 2007).
14. LIN, W., AND CHANG, L. Dual greedy: Adaptive garbage collection for page-mapping solid-state disks. In Design, Automation & Test in Europe Conf. & Exhibition (Dresden, Germany, Mar. 2012), pp. 117–22.
15. LIU, R., YANG, C., AND WU, W. Optimizing NAND flash-based SSDs via retention relaxation. Target 11, 10 (2012).
16. LUE, H.-T., DU, P.-Y., CHEN, C.-P., CHEN, W.-C., HSIEH, C.-C., HSIAO, Y.-H., SHIH, Y.-H., AND LU, C.-Y. Radically extending the cycling endurance of flash memory (to >100M cycles) by using built-in thermal annealing to self-heal the stress-induced damage. In IEEE Int. Electron Devices Meeting (San Francisco, California, USA, Dec. 2012), pp. 9.1.1–4.
17. MICHELONI, R., CRIPPA, L., AND MARELLI, A. Inside NAND Flash Memories. Springer, 2010.
18. MOHAN, V., SIDDIQUA, T., GURUMURTHI, S., AND STAN, M. R. How I learned to stop worrying and love flash endurance. In Proc. USENIX Conf. Hot Topics in Storage and File Systems (Boston, Massachusetts, USA, June 2010).
19. NARAYANAN, D., DONNELLY, A., AND ROWSTRON, A. Write off-loading: Practical power management for enterprise storage. In Proc. USENIX Conf. File and Storage Technologies (San Jose, California, USA, Feb. 2008), pp. 253–67.
20. PAN, Y., DONG, G., AND ZHANG, T. Error rate-based wear-leveling for NAND flash memory at highly scaled technology nodes. IEEE Trans. Very Large Scale Integration Systems 21, 7 (July 2013), 1350–54.
21. PARK, D., DEBNATH, B., NAM, Y., DU, D. H. C., KIM, Y., AND KIM, Y. HotDataTrap: a sampling-based hot data identification scheme for flash memory. In ACM Int. Symp. Applied Computing (Riva del Garda, Italy, Mar. 2012), pp. 1610–17.
22. PARK, J.-W., PARK, S.-H., WEEMS, C. C., AND KIM, S.-D. A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk. Microprocessors & Microsystems 35, 1 (Feb. 2011), 48–59.
23. SCHWARZ, T., XIN, Q., MILLER, E., LONG, D. D. E., HOSPODOR, A., AND NG, S. Disk scrubbing in large archival storage systems. In IEEE Int. Symp. Modeling, Analysis, and Simulation of Computer and Telecommunications Systems (Volendam, Netherlands, Oct. 2004), pp. 409–18.
24. WANG, C., AND WONG, W.-F. Extending the lifetime of NAND flash memory by salvaging bad blocks. In Design, Automation & Test in Europe Conf. & Exhibition (Dresden, Germany, Mar. 2012), pp. 260–63.
25. WU, M., AND ZWAENEPOEL, W. eNVy: a non-volatile, main memory storage system. In Sixth Int. Conf. on Architectural Support for Programming Languages and Operating Systems (San Jose, California, USA, Oct. 1994), pp. 86–97.
26. ZAMBELLI, C., INDACO, M., FABIANO, M., DI CARLO, S., PRINETTO, P., OLIVO, P., AND BERTOZZI, D. A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories. In Design, Automation & Test in Europe Conf. & Exhibition (Dresden, Germany, 2012), pp. 881–86.