PEST-A tool for implementing pseudo-exhaustive self test

Proceedings of the European Design Automation Conference, EDAC 1990

Volumn , Issue , 1990, Pages 639-643

  Wu, Eleanor ^a   Rutkowski, Paul W ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS;

FAULT COVERAGES; FAULT SIMULATION; NETWORK INTERFACE CONTROLLERS; PARALLEL TESTING; TEST GENERATION ALGORITHM; TEST GENERATIONS; TEST POINT SELECTION; TEST VECTOR GENERATIONS;

COMPUTER AIDED DESIGN;

EID: 84977303789     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDAC.1990.136724     Document Type: Conference Paper

References (11)

1. S. B. Akers, "On the use of linear sums in exhaustive testing, " in Proc. 15th International Conference on Fault-Tolerant Computing, pp. 148-153, June 1985.
2. E. C. Archambeau, E.J. McCluskey, "Fault coverage of pseudo-exhaustive testing, " Proc. 14th International Conference on Fault-Tolerant Computing, pp. 141-145, July 1984.
3. E. Barzilai, D. Coppersmith., A. L. Rosenberg, "Exhaustive generation of bit patterns with applications to VLSI Self-Testing, " IEEE Transactions on Comput-ers.VOL C-32, No. 2, February 1983.
4. H. Cox, A. Ivanov, V.K. Agarwal, J. Rajski, "On multiple fault coverage and aliasing probability measures, " Proc. International Test Conference, pp. 314-321, Sept. 1988.
5. E. J. McCluskey, "Pseudo-exhaustive testing for VLSI devices, " Proc. ATE Silicon Valley, April 1984.
6. E. J. McCluskey, "Verification testing-A pseudo-exhaustive testing technique, " IEEE Transactions on Computers, VOL. c-33, No. 6, pp. 541-546, June 1984.
7. M. W. Roberts and P. K. Lala, "An algorithm for the partitioning of logic circuits, " IEE Proc, VOL. 131, Pt. E, No. 4, July 1984.
8. I. Shperling and E. J. McCluskey, "Circuit segmentation for pseudo-exhaustive testing via simulated annealing, " Proc. International Test Conference, pp. 58-66, Sept. 1987.
9. D. T. Tang, L. S. Woo, "Exhaustive test pattern generation with constant weight vectors, " IEEE Transactions on Computers, VOL c-32, No. 12, pp. 1145-1150, December 1983.
10. D. T. Tang, C. C. Chen, "Logic test pattern generation using linear codes, " IEEE Transactions on computers, VOL. c-33, No. 9, pp. 845-849, September 1984.
11. Nagesh Vasanthavada, Peter N. Marinos, "An operationally efficient scheme for exhaustive test-pattern generation using linear codes" Proc. of the 1985 Int. Test Conference, pp. 476-482, September 1986.