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Volumn 29, Issue 11, 1994, Pages 158-170

Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches

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Indexed keywords


EID: 84976728253     PISSN: 03621340     EISSN: 15581160     Source Type: Journal    
DOI: 10.1145/195470.195527     Document Type: Article
Times cited : (55)

References (28)
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    • Dutton, T.1    Eiref, D.2    Kurth, H.3    Reisert, J.4    Stewart, R.5
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    • PhD dissertation, University of California at Berkeley, Computer Sciences Division, November Number UCB/CSD 87/381
    • Hill, M. D. Aspects of Cache Memory and Instruction Buffer Performance. PhD dissertation, University of California at Berkeley, Computer Sciences Division, November 1987. Number UCB/CSD 87/381.
    • (1987) Aspects of Cache Memory and Instruction Buffer Performance
    • Hill, M.D.1
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    • A Case for Direct-Mapped Caches
    • December
    • Hill, M. D. A Case for Direct-Mapped Caches. IEEE Computer, pages 25-40, December 1988.
    • (1988) IEEE Computer , pp. 25-40
    • Hill, M.D.1
  • 15
    • 0025429331 scopus 로고
    • Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
    • May
    • Jouppi, N. P. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. In Proceedings of the 17th Annual International Symposium On Computer Architecture, pages 364-373, May 1990.
    • (1990) Proceedings of the 17th Annual International Symposium On Computer Architecture , pp. 364-373
    • Jouppi, N.P.1
  • 16
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    • Prentice-Hall, Englewood Cliffs, NJ
    • Kane, G. MIPS RISC Architecture. Prentice-Hall, Englewood Cliffs, NJ, 1988.
    • (1988) MIPS RISC Architecture
    • Kane, G.1
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    • Page Placement Algorithms for Large Real-Indexed Caches
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    • Kessler, R. and Hill, M. D. Page Placement Algorithms for Large Real-Indexed Caches. ACM Transactions on Computer Systems, 10(4):338-359, November 1992.
    • (1992) ACM Transactions on Computer Systems , vol.10 , Issue.4 , pp. 338-359
    • Kessler, R.1    Hill, M.D.2
  • 18
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    • DeLano,?., and Bryg, W. PA7200: A PARISC Processor with Integrated High Performance MP Bus Interface
    • Kurpanek, G., Chan, K., Zheng, J., DeLano,?., and Bryg, W. PA7200: A PARISC Processor with Integrated High Performance MP Bus Interface. In Digest of Papers. Spring COMPCON 94, pages 375-382, 1994.
    • (1994) Digest of Papers. Spring COMPCON , vol.94 , pp. 375-382
    • Kurpanek, G.1    Chan, K.2    Zheng, J.3
  • 22
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.