Fault tolerant Hopfield associative memory on torus

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 369-376

  Ayoubi, R A ^a   Ziade, H A ^b   Bayoumi, M A ^c  

^a UNIVERSITY OF BALAMAND   (Lebanon)

^b LEBANESE UNIVERSITY   (Lebanon)

^c University of Louisiana at Lafayette   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ASSOCIATIVE PROCESSING; COMBINATORIAL OPTIMIZATION; COMPLEX NETWORKS; COST EFFECTIVENESS; DEFECTS; MEMORY ARCHITECTURE; NETWORK ARCHITECTURE; NEURAL NETWORKS; OPTIMIZATION; PARALLEL ARCHITECTURES; PATTERN RECOGNITION;

ASSOCIATIVE MEMORY; COMBINATORIAL OPTIMIZATION PROBLEMS; COMPLEX ARCHITECTURES; FAULT TOLERANT ALGORITHMS; FAULT-TOLERANT; HARDWARE OVERHEADS; HOPFIELD ANN; NOISE REMOVAL;

FAULT TOLERANCE;

EID: 84971280936     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250133     Document Type: Conference Paper

References (17)

1. J. J Hopfield, "Neurons with graded response have collective computational properties like those of twostate neurons", in Proceedings of the National Academy of Sciences, vol. 81, pp. 3080-3092, 1984.
2. G. R. Bolt, "Fault models for artificial networks", in Proceedings of International Joint Conference on Neural Networks, vol. 3, (Singapore), pp. 1918-1923, 1991.
3. C. Neti, M. H. Schneider, and E. D. Young, "Maximally fault tolerant neural networks", IEEE Transactions on Neural Networks, vol. 3, no. 1, pp. 14-23, 1992.
4. K. Matsuoka, "Noise injection into inputs in back-propagation learning", IEEE Transactions on Systems, Man, and Cybernetics, vol. 22, no. 3, pp. 436-440, 1992.
5. C. H. Sequin and R. D. Clay, "Fault tolerance in artificial neural networks", in Proceedings of International Joint Conference on Neural Networks, vol. 1, (San Diego, CA), pp. 703-708, 1990.
6. M. D. Emmerson and R. I. Damper, "Determining and improving the fault tolerance of multilayer perceptrons in a pattern-recognition application", IEEE Transactions on Neural Networks, vol. 4, no. 5, pp. 788-793, 1993.
7. A. Avizienis, "Fault-tolerance: The survival attribute of digital systems", in Proceedigns of the IEEE, vol. 66, pp. 1109-1125, 1978.
8. J. Wakerly, Error-Detecting Codes, Self-Checking Circuits and Applications. Amsterdam: Elsevier, 1978.
9. P.-J. Chuang and N.-F. Tzeng, "Allocating precise submeshes in mesh connected systems", IEEE Transactions on Parallel and Distributed Systems, vol. 5, no. 2, pp. 211-217, 1994.
10. K.-H. Huang and J. A. Abraham, "Algorithm-based fault tolerance for matrix operations", IEEE Transactions on Computers, vol. C-33, no. 6, pp. 518-528, 1984.
11. Y. Kim, M. J. Noh, T. D. Han, and S. D. Kim, "Mapping of neutral networks onto the memory processor integrated architecture", Neutral Networks, vol. 11, pp. 1083-1098, 1998.
12. W. Lin, V. K. Prasanna, and K. W. Przytula, "Algorithmic mapping of neutral network models onto parallel SIMD machines", IEEE Transactions on Computers, vol. 40, no. 12, pp: 1390-1401, 1991.
13. S. Shams and J. L. Gaudiot, "Implementing regularly structure neural networks on the DREAM machine", IEEE Transactions on neural networks, vol. 6, no. 2, pp. 407-421, 1995.
14. S. Shams and W. Przytula, "Mapping of neutral network onto programmable parallel machines", in Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2613-2617, New Orleans, LA, 1990.
15. Y. Kim, M. J. Noh, T. D. Han, and S. D. Kim, "Mapping of neutral networks onto the memory processor integrated architecture", Neutral Networks, vol. 11, pp. 1083-1098, 1998.
16. R. A. Ayoubi and M. A. Bayoumi, "An efficient implementation of multilayer percetrpon on mesh architecture", in Proceedings of IEEE International Symposium on Circuits and Systems, 2:109-112, Scottsdale, Arizona, 2002.
17. Q. M. Malluhi, M. A. Bayouni, and T. R. N. Rao, "Efficient mapping of ANNs on hypercube massively parallel machine", IEEE Transactions on Computers, vol. 44, no. 6, pp. 769-779, 1995.