FPGA based controller for heterogenous image processing system

Proceedings - Euromicro Symposium on Digital Systems Design: Architectures, Methods and Tools, DSD 2001

Volumn , Issue , 2001, Pages 453-457

  Gorgon, M ^a   Pryzybylo, J ^a  

^a AGH UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROLLERS; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE ACQUISITION; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS;

COMMUNICATION RESOURCES; CONTROL CENTRE; FLOATING POINTS; FPGA DEVICES; FPGA-BASED CONTROLLER; IMAGE PROCESSING SYSTEM; MOTOROLA; REAL TIME;

IMAGE PROCESSING;

EID: 84969567808     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2001.952366     Document Type: Conference Paper

References (15)

1. PRATT W.K., Digital Image Processing, John Wiley & Sons, Inc., 1991.
2. RITTER, G. X., WILSON, J.N., Computer Vision Algorithms in Image Algebra, CRC Press Inc.,Boca Raton, USA, 1996.
3. ULLMAN, S., High-level Vision, The MIT Press 1997
4. UMBAUGH, S. E., Computer Vision and Image Processing, Prentice Hall International, Inc., 1998.
5. TADEUSIEIWICZ, R. The multiprocessors architectures for image processing, Lecture Notes on Computer Vision and Artificial Intelligence, Warszawa, pp. 226-269, 1989.
6. KUNG, S.Y., VLSI Array Processors, Prentice Hall, New Jersey 1989.
7. JONKER, P.P., Morphological Image Processing: Architecture and VLSI design, Delft University of Technology, 1992.
8. LANGE, A.A.J., Design and Implementation of Highly Parallel Pipelined VLSI System, Delft University of Technology, 1991.
9. DAGLESS, E. at al., Image Processing Hardware, Proc. of the 5-th School Computer Vision and Graphics Zakopane, Wyd. Format Wrocaw 1994.
10. SOREL, Y., Real - Time Embedded Image Processing Applications using the A3 Methodology, Proc. of ICIP - 96, IEEE 1996.
11. GAJER, M., Image Processing and Recognition on the TMS320C80 Multiprocessor System, Proc. of 6th international Conference Mixeds'99, Krakw, Poland 1999.
12. WIATR, K., Pipelined architecture of Reconfigurable Specialised Processors for a Real-Time Image Data Pre-Processing, Proc. of ICIP, IEEE Press 96TH8116, vol.1, pp. 649-652, Bejing, China, 1996.
13. GORGON, M.Universal Reprogrammable Architecture for Implementation Dedicated Image Processors Based on FPGA. Proc. of Sixth International Conference on Image Processing and its Applications IPA 97, Trinity College, Dublin, Ireland 14-17 July 1997, IEE Conference Publication no.: 443, vol.2, pp. 556-560.
14. ZAPATA, R., at all, Integration of biologically-plausible vision systems for controlling autonomous robots, SPIE Proceedings, vol. 4212, Boston, USA, 2000.
15. XUE, J., at all, An approach to constructing reconfigurable computer vision system, SPIE Proceedings, vol 4212, Boston, USA, 2000.