Non-recursive switch ed-capacitor decimator and interpolator circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1992, Pages 1215-1218

  Wu, Chung Yu ^a   Huang, Shou Yuan ^a   Yu, Tsai Chung ^a   Shieu, Yie Yuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

SENSITIVITY ANALYSIS; TIMING CIRCUITS;

CIRCUIT STRUCTURES; CLOCK PHASIS; DESIGN PROCEDURE; DYNAMIC RANGE; LOW SENSITIVITY; NOISE PERFORMANCE; POWER SUPPLY VARIATIONS; SWITCHED CAPACITOR;

INTERPOLATION;

EID: 84968995663     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.1992.230306     Document Type: Conference Paper

References (7)

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7. T.-C. Yu, C.-Y. Wu, and S.-S. Chang, " Realizations of IIR/FIR and N-path filters using a novel switched-capacitor technique, " IEEE Trans. on CAS, vol. 37, no. 1, pp. 91-106, Jan. 1990.