Pipelined fast 2D DCT architecture for JPEG image compression

Proceedings - 14th Symposium on Integrated Circuits and Systems Design, SBCCI 2001

Volumn , Issue , 2001, Pages 226-231

  Agostini, L V ^b   Silva, I S ^a   Bampi, S ^b  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO NORTE   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE CODING; IMAGE COMPRESSION; INTEGRATED CIRCUITS; LOGIC DEVICES; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS;

CLOCK CYCLES; CRITICAL PATHS; JPEG COMPRESSION; JPEG-IMAGE COMPRESSION; OPERATING FREQUENCY; PIPELINE LATENCY; TWO DIMENSIONAL DISCRETE COSINE TRANSFORM; VHDL SYNTHESIS;

DISCRETE COSINE TRANSFORMS;

EID: 84966267494     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2001.953032     Document Type: Conference Paper

References (13)

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