Integration of passive and active components into build-up layers

Proceedings of 4th Electronics Packaging Technology Conference, EPTC 2002

Volumn , Issue , 2002, Pages 223-228

  Ostmann, A ^a   Neumann, A ^b   Auersperg, J ^a   Ghahremani, C ^a   Sommer, G ^a   Aschenbrenner, R ^a   Reichl, H ^b  

^a FRAUNHOFER IZM   (Germany)

^b TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; MICROELECTRONICS; PRINTED CIRCUIT BOARDS; PRINTED CIRCUITS; PRODUCT DESIGN;

ADVANCED PACKAGING; ELECTRONIC SYSTEMS; INTEGRATED PASSIVE COMPONENTS; INTEGRATED RESISTORS; INTERCONNECTION TECHNOLOGY; MICROELECTRONIC PACKAGING; OPERATING FREQUENCY; THERMOMECHANICAL PROPERTIES;

CHIP SCALE PACKAGES;

EID: 84964619877     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2002.1185672     Document Type: Conference Paper

References (12)

1. R. Filion, R. Wojnarowski, T. Gorcyzca, B. Wildi, H. Cole; "Development of a Plastic Encapsulated Multichip Technology for High Volume, Low Cost Commercial Electronics", 10. Applied Power Electronics Conf, IEEE, 1994, pp. 805-809.
2. Owzar, K. Buschik, O. Ehrmann; M. Kasper; "RF-Investigation of the electrical parameters of the embedded chip structure", Proc. VLSI Packaging Workshop, Monterey USA, October 16-18, (1995).
3. T. Waris, R. Tuominen, J. Kivilahti, "Panel-sized Integrated Module Board Manufacturing", Proc. Polytronic Conference, Oct. 21. - 24. 2001, Potsdam, Germany.
4. B. Klose, "Chip-first Systeme und -Gehäuse", PhD Thesis, University Siegen, Germany 1999.
5. H. Braunisch, S. Towle, R. Emery, C. Hu and G. Vandentop, "Electrical Performance of Bumpless Build-Up Layer Packaging", Proc. ECTC 2002, May 28. - 31. 2002,San Diego, USA.
6. Auersperg, J., Kieselstein, E., Schubert, A., Michel, B., "Mixed Mode Interfacial Fracture Toughness Evaluation for Flip-Chip Assemblies and CSP Based on Fracture Mechanics Approaches", Symp. on Reliability, Stress Analysis, and Failure Prevention of the 2001 ASME International Mechanical Engineering Congress and Exposition, November 11-16, 2001, New York, proc. Vol. 2, IMECE2001/DE-25109
7. J.-C. Sanchez "Wafer thinning and stress release", Proc. Workshop on Ultra-thin Silicon Packaging at Fraunhofer ISIT, September 26 2002, Itzehoe, Germany.
8. Ch. Scheiring, "Automated bonding of ultra-thin dice", Proc. Workshop on Ultra-thin Silicon Packaging at Fraunhofer ISIT, September 26 2002, Itzehoe, Germany.
9. A. Ostmann, A. Neumann, S. Weser, E. Jung, L. Böttcher and H. Reichl, "Realization of a Stackable Package Using Chip in Polymer Technology", Polytronic Conference, June 23.-26. 2002, Zalaegerszeg, Hungary
10. G. Sommer, W. John, I. Dörr, M. Vakilzadeh, H. Reichl; "Workflow for RF Modeling of Chip Packages for High Density System Development", High Density packaging and Component Failure Analysis (HDP) 2000, Proceedings of 00' International Symposium on Electronic Packaging, December 2000
11. E. Jan Vardaman, Frank Bachner, Doug Feicht; "High Density Microvia Substrates: Markets, Applications, and Infrastructure", 1999 TechSearch International, Inc, 4801 Spicewood Springs Road, Suite 150, Austin, Texas 78759, July 1999
12. Auersperg, J., Dudek, R., Michel, B., "Parameterized FE-Modeling and Interfacial Fracture Toughness Investigations Towards Reliability Enhancements of Advanced Plastic Packages", held on Symp. on Design, Test, Integration and Packaging of MEMS/MOEMS of the DTIP 2002 Conf. of MEMS/MOEMS, Cannes-Mandelieu, France, 6-8 May 2002