Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2016-February, Issue , 2015, Pages 17.2.1-17.2.4

  Piccolboni, G ^a   Molas, G ^a   Portal, J M ^b   Coquand, R ^a   Bocquet, M ^b   Garbin, D ^a   Vianello, E ^a   Carabasse, C ^a   Delaye, V ^a   Pellissier, C ^a   Magis, T ^a   Cagli, C ^a   Gely, M ^a   Cueto, O ^a   Deleruyelle, D ^b   Ghibaudo, G ^c   De Salvo, B ^a   Perniola, L ^a  

^a CEA GRENOBLE   (France)

^b AIX MARSEILLE UNIVERSITÉ   (France)

^c IMEP LAHC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX NETWORKS; COST EFFECTIVENESS; DIGITAL STORAGE; ELECTRON DEVICES; NETWORKS (CIRCUITS); RANDOM ACCESS STORAGE; RECONFIGURABLE HARDWARE;

COMPLEX CIRCUITS; COST EFFECTIVE; MASS DATA; NEUROMORPHIC; NEUROMORPHIC CIRCUITS; PLANAR DEVICES; TECHNOLOGY AND DESIGNS;

RRAM;

EID: 84964091883     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2015.7409717     Document Type: Conference Paper

References (8)

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2. I. T. Wang et al., 2014 IEDM Tech. Dig., pp.665-668.
3. M. Suri et al., IEDM 2012 Tech. Dig., pp.235-238.
4. D. Garbin et al., IEDM 2014 Tech. Dig., pp. 661-664.
5. A. Calderoni et al., proc. of IMW 2014.
6. M. Bocquet et al., IEEE Trans. on Elec. Dev. 61, 3, 674-681, 2014
7. M. Suri et al., IEEE Trans. on Elec. Dev. 60, 7, 2402-24409, 2013.
8. D. Garbin et al., IEEE Trans. on Elec. Dev., 2015.