Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2016-February, Issue , 2015, Pages 34.5.1-34.5.4

  Avci, Uygar E ^a   Chu Kung, Benjamin ^a   Agrawal, Ashish ^a   Dewey, Gilbert ^a   Le, Van ^a   Rios, Rafael ^a   Morris, Daniel H ^a   Hasan, Sayed ^a   Kotlyar, Roza ^a   Kavalieros, Jack ^a   Young, Ian A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION; DEFECT DENSITY; ELECTRON DEVICES; FIELD EFFECT TRANSISTORS; GEOMETRY; GERMANIUM; SEMICONDUCTOR DIODES;

CURRENT COMPONENT; INTERFACE DEFECTS; INTERFACE EFFECT; OPTIMIZED GEOMETRIES; OXIDE INTERFACES; TEMPERATURE CHARACTERIZATION; TRAP ASSISTED TUNNELING; TUNNELING FIELD-EFFECT TRANSISTORS;

DEFECTS;

EID: 84964088518     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2015.7409828     Document Type: Conference Paper

References (9)

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4. MG. Pala et al, TED 2013, pp. 2795.
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6. A. Schenk, Solid State Electronics, 1992, pp. 1585.
7. G.A.M. Hurkx, et al, TED 1992 pp. 2090.
8. S. Agarwal, et al, TED 2014, pp. 1488.
9. Y.-Y. Chen, EDL 2013, pp. 444.