Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2016-February, Issue , 2015, Pages 4.1.1-4.1.4

  Eryilmaz, S Burc ^a   Kuzum, Duygu ^b   Yu, Shimeng ^c   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; DIGITAL STORAGE; ELECTRON DEVICES;

BRAIN-INSPIRED COMPUTING; CYCLE TO CYCLE VARIATION; DESIGN CONSIDERATIONS; DESIGN DECISIONS; LEARNING PERFORMANCE; NEUROMORPHIC ARCHITECTURES; NON-VOLATILE MEMORY; SYSTEM LEVEL DESIGN;

DESIGN;

EID: 84964031980     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2015.7409622     Document Type: Conference Paper

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