An Efficient Content-Addressable Memory Implementation Using Dynamic Routing

Proceedings - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001

Volumn , Issue , 2001, Pages 81-90

  James Roxby, P B ^a   Downs, D J ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; TELECOMMUNICATION INDUSTRY;

DESIGN FLOWS; DYNAMIC ROUTING; EXPERIMENTAL SET UP; HIGH-SPEED NETWORKING; IPV6 TRAFFIC; PRIORITY ENCODER; SORTING NETWORK; STANDARD DESIGN;

ASSOCIATIVE STORAGE;

EID: 84963966432     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Altera Corp. : "Implementing high speed search applications with APEX CAM", Application note 119, available on line at http://www.altera.com/document/an/an119.pdf
2. Xilinx, Inc. : "An overview of multiple CAM designs in Virtex devices", Application note XAPP201, available on line at http://www.xilinx.com/xapp/xapp201.pdf
3. Brebner, G. and Bergmann, N. : "Reconfigurable computing in remote and harsh environments", in Lysaght, Irvine and Hartenstein (Eds) , FPL99, LNCS 1673, pp 195-204
4. Ditmar, J., Torkelson, K. and Jantsch, A. : "A dynamically reconfigurable FPGA-based content addressable memory for internet protocol characterization", in Hartenstein and Gruenbacher (Eds), FPL00, LNCS 1896, pp 19-28
5. Guccione, S., Levi, D. and Downs, D. : "A reconfigurable content addressable memory", in J Rolim et al (Eds): ISPDS2000 Workshops (RAW2000), LNCS 1800, pp882-889, 2000
6. James-Roxby, P. and Guccione, S. : "Automated extraction of run-time parameterisable cores from programmable device configurations", in Pocek and Arnold (Eds), Field-programmable custom computing machines, Proc. of FCCM2000, Napa Valley, CA
7. Xilinx, Inc : "Virtex 2.5V Field Programmable Gate Arrays : Product specification"
8. Brebner, G. and Donlin, A. : "Run-time reconfigurable routing", Proc. RAW98
9. Keller, E. : : "JRoute: A run-time routing API for FPGA hardware", in Jose Rolim et al, Editors, Parallel and Distributed Processing, Proc. of RAW2000, Cancun, Mexico, pp 874-881
10. McMillan, S. and Guccione, S.: "Partial Run-Time Reconfiguration Using JRTR", in Hartenstein and Gruenbacher (Eds), FPL00, LNCS 1896, pp 352-360