메뉴 건너뛰기




Volumn 35, Issue 3, 2016, Pages 433-446

Accelerating architectural simulation via statistical techniques: A survey

Author keywords

Architectural simulation; Design space exploration; Regression; Statistical methods

Indexed keywords

ARCHITECTURAL DESIGN; COMPUTER ARCHITECTURE; SIMULATORS; SURVEYS;

EID: 84963747320     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2015.2481796     Document Type: Article
Times cited : (15)

References (122)
  • 1
    • 33947433665 scopus 로고    scopus 로고
    • The future of simulation: A field of dreams
    • Nov.
    • J. J. Yi et al., "The future of simulation: A field of dreams," Computer, vol. 39, no. 11, pp. 22-29, Nov. 2006.
    • (2006) Computer , vol.39 , Issue.11 , pp. 22-29
    • Yi, J.J.1
  • 2
    • 27544478808 scopus 로고    scopus 로고
    • Mambo: A full system simulator for the PowerPC architecture
    • Mar.
    • P. Bohrer et al., "Mambo: A full system simulator for the PowerPC architecture," ACM SIGMETRICS Perform. Eval. Rev., vol. 31, no. 4, pp. 8-12, Mar. 2004.
    • (2004) ACM SIGMETRICS Perform. Eval. Rev. , vol.31 , Issue.4 , pp. 8-12
    • Bohrer, P.1
  • 3
    • 84963782060 scopus 로고    scopus 로고
    • PowerPC 405GP Embedded Processor Users Manual, IBM Corp., Research Triangle Park, NC, USA
    • PowerPC 405GP Embedded Processor Users Manual, IBM Corp., Research Triangle Park, NC, USA, 2000.
    • (2000)
  • 4
    • 52249092748 scopus 로고    scopus 로고
    • SimNow: Fast platform simulation purely in software
    • Aug. [Online]
    • R. Bedicheck, "SimNow: Fast platform simulation purely in software," in Proc. Hot Chips, Aug. 2004. [Online]. Available: http://www.hotchips.org/wp-content/uploads/hc-archives/hc16/2-Mon/ 15-HC16-Sess4-Pres1-bw.pdf
    • (2004) Proc. Hot Chips
    • Bedicheck, R.1
  • 5
    • 79955891472 scopus 로고    scopus 로고
    • HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
    • San Antonio, TX, USA
    • M. Pellauer, M. Adler, M. Kinsy, A. Parashar, and J. Emer, "HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing," in Proc. HPCA, San Antonio, TX, USA, 2011, pp. 406-417.
    • (2011) Proc. HPCA , pp. 406-417
    • Pellauer, M.1    Adler, M.2    Kinsy, M.3    Parashar, A.4    Emer, J.5
  • 6
    • 84856201867 scopus 로고    scopus 로고
    • Graphite: A distributed parallel simulator for multicores
    • Bengaluru, India
    • J. E. Miller et al., "Graphite: A distributed parallel simulator for multicores," in Proc. HPCA, Bengaluru, India, 2010, pp. 1-12.
    • (2010) Proc. HPCA , pp. 1-12
    • Miller, J.E.1
  • 7
    • 77952559926 scopus 로고    scopus 로고
    • Interval simulation: Raising the level of abstraction in architectural simulation
    • Bengaluru, India
    • D. Genbrugge, S. Eyerman, and L. Eeckhout, "Interval simulation: Raising the level of abstraction in architectural simulation," in Proc. HPCA, Bengaluru, India, 2010, pp. 1-12.
    • (2010) Proc. HPCA , pp. 1-12
    • Genbrugge, D.1    Eyerman, S.2    Eeckhout, L.3
  • 8
    • 83155173614 scopus 로고    scopus 로고
    • Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation
    • Seatle, WA, USA
    • T. E. Carlson, W. Heirman, and L. Eeckhout, "Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation," in Proc. SC, Seatle, WA, USA, 2011, pp. 1-12.
    • (2011) Proc. SC , pp. 1-12
    • Carlson, T.E.1    Heirman, W.2    Eeckhout, L.3
  • 9
    • 70349735560 scopus 로고    scopus 로고
    • Parallelization of IBM mambo system simulator in functional modes
    • Jan.
    • K. Wang, Y. Zhang, H. Wang, and X. Shen, "Parallelization of IBM mambo system simulator in functional modes," SIGOPS Oper. Syst. Rev., vol. 42, no. 1, pp. 71-76, Jan. 2008.
    • (2008) SIGOPS Oper. Syst. Rev. , vol.42 , Issue.1 , pp. 71-76
    • Wang, K.1    Zhang, Y.2    Wang, H.3    Shen, X.4
  • 10
    • 77952555923 scopus 로고    scopus 로고
    • SlackSim: A platform for parallel simulations of CMPs on CMPs
    • May
    • J. Chen, M. Annavaram, and M. Dubois, "SlackSim: A platform for parallel simulations of CMPs on CMPs," ACM SIGARCH Comput. Archit. News, vol. 37, no. 2, pp. 20-29, May 2009.
    • (2009) ACM SIGARCH Comput. Archit. News , vol.37 , Issue.2 , pp. 20-29
    • Chen, J.1    Annavaram, M.2    Dubois, M.3
  • 11
    • 47349112481 scopus 로고    scopus 로고
    • FPGA-accelerated simulation technologies (FAST): Fast, full-system, cycle-accurate simulators
    • Chicago, IL, USA
    • D. Chiou et al., "FPGA-accelerated simulation technologies (FAST): Fast, full-system, cycle-accurate simulators," in Proc. MICRO, Chicago, IL, USA, 2007, pp. 249-261.
    • (2007) Proc. MICRO , pp. 249-261
    • Chiou, D.1
  • 12
    • 77952560029 scopus 로고    scopus 로고
    • ProtoFlex: Towards scalable, full-system multiprocessor simulations using FPGAs
    • Jun.
    • E. S. Chung et al., "ProtoFlex: Towards scalable, full-system multiprocessor simulations using FPGAs," ACM Trans. Reconfig. Tech. Syst., vol. 2, no. 2, Jun. 2009, Art. ID 15.
    • (2009) ACM Trans. Reconfig. Tech. Syst. , vol.2 , Issue.2
    • Chung, E.S.1
  • 13
    • 77956220100 scopus 로고    scopus 로고
    • RAMP gold: An FPGA-based architecture simulator for multiprocessors
    • Anaheim, CA, USA
    • Z. Tan et al., "RAMP gold: An FPGA-based architecture simulator for multiprocessors," in Proc. DAC, Anaheim, CA, USA, 2010, pp. 463-468.
    • (2010) Proc. DAC , pp. 463-468
    • Tan, Z.1
  • 15
    • 67650754372 scopus 로고    scopus 로고
    • C++ benchmarks in SPEC CPU2006
    • Mar.
    • M. Wong, "C++ benchmarks in SPEC CPU2006," SIGARCH Comput. Archit. News CAN, vol. 35, no. 1, pp. 77-83, Mar. 2007.
    • (2007) SIGARCH Comput. Archit. News CAN , vol.35 , Issue.1 , pp. 77-83
    • Wong, M.1
  • 16
    • 79957528059 scopus 로고    scopus 로고
    • Trace-driven simulation of multithreaded applications
    • Austin, TX, USA
    • A. Rico et al., "Trace-driven simulation of multithreaded applications," in Proc. ISPASS, Austin, TX, USA, 2011, pp. 87-96.
    • (2011) Proc. ISPASS , pp. 87-96
    • Rico, A.1
  • 17
    • 0003465202 scopus 로고    scopus 로고
    • Dept. Comput. Sci., Univ. Wisconsin-Madison, Madison, WI, USA, Tech. Rep. Jun.
    • D. Burger and T. M. Austin, "The SimpleScalar tool set, version 2.0," Dept. Comput. Sci., Univ. Wisconsin-Madison, Madison, WI, USA, Tech. Rep. 1342, Jun. 1997.
    • (1997) The SimpleScalar Tool Set, Version 2.0 , vol.1342
    • Burger, D.1    Austin, T.M.2
  • 18
    • 0036470602 scopus 로고    scopus 로고
    • Rsim: Simulating shared-memory multiprocessors with ILP processors
    • Feb.
    • C. J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve, "Rsim: Simulating shared-memory multiprocessors with ILP processors," Computer, vol. 35, no. 2, pp. 40-49, Feb. 2002.
    • (2002) Computer , vol.35 , Issue.2 , pp. 40-49
    • Hughes, C.J.1    Pai, V.S.2    Ranganathan, P.3    Adve, S.V.4
  • 19
    • 0036469676 scopus 로고    scopus 로고
    • Simics: A full system simulation platform
    • Feb.
    • P. S. Magnusson et al., "Simics: A full system simulation platform," Computer, vol. 35, no. 2, pp. 50-58, Feb. 2002.
    • (2002) Computer , vol.35 , Issue.2 , pp. 50-58
    • Magnusson, P.S.1
  • 20
    • 33748870886 scopus 로고    scopus 로고
    • Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
    • Nov.
    • M. M. K. Martin et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Comput. Archit. News, vol. 33, no. 4, pp. 92-99, Nov. 2005.
    • (2005) SIGARCH Comput. Archit. News , vol.33 , Issue.4 , pp. 92-99
    • Martin, M.M.K.1
  • 21
    • 84859464490 scopus 로고    scopus 로고
    • The gem5 simulator
    • May
    • N. Binkert et al., "The gem5 simulator," SIGARCH Comput. Archit. News, vol. 39, no. 2, pp. 1-7, May 2011.
    • (2011) SIGARCH Comput. Archit. News , vol.39 , Issue.2 , pp. 1-7
    • Binkert, N.1
  • 22
    • 33846535493 scopus 로고    scopus 로고
    • The M5 simulator: Modeling networked systems
    • Jul./Aug.
    • N. L. Binkert et al., "The M5 simulator: Modeling networked systems," IEEE Micro, vol. 26, no. 4, pp. 52-60, Jul./Aug. 2006.
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 52-60
    • Binkert, N.L.1
  • 23
    • 80052679723 scopus 로고    scopus 로고
    • MARSS: A full system simulator for multicore x86 CPUs
    • New York, NY, USA
    • A. Patel, F. Afram, S. Chen, and K. Ghose, "MARSS: A full system simulator for multicore x86 CPUs," in Proc. DAC, New York, NY, USA, 2011, pp. 1050-1055.
    • (2011) Proc. DAC , pp. 1050-1055
    • Patel, A.1    Afram, F.2    Chen, S.3    Ghose, K.4
  • 24
    • 36949014308 scopus 로고    scopus 로고
    • PTLsim: A cycle accurate full system x86-64 microarchitectural simulator
    • San Jose, CA, USA
    • M. T. Yourst, "PTLsim: A cycle accurate full system x86-64 microarchitectural simulator," in Proc. ISPASS, San Jose, CA, USA, 2007, pp. 23-34.
    • (2007) Proc. ISPASS , pp. 23-34
    • Yourst, M.T.1
  • 25
    • 31944440969 scopus 로고    scopus 로고
    • Pin: Building customized program analysis tools with dynamic instrumentation
    • Chicago, IL, USA
    • C.-K. Luk et al., "Pin: Building customized program analysis tools with dynamic instrumentation," in Proc. PLDI, Chicago, IL, USA, 2005, pp. 190-200.
    • (2005) Proc. PLDI , pp. 190-200
    • Luk, C.-K.1
  • 26
    • 77949710964 scopus 로고    scopus 로고
    • CMP$im: A pin-based on-the-fly multi-core cache simulator
    • Beijing, China Jun. [Online]
    • A. Jaleel, R. S. Cohn, C.-K. Luk, and B. Jacob, "CMP$im: A pin-based on-the-fly multi-core cache simulator," in Proc. MOBS, Beijing, China, Jun. 2008. [Online]. Available: http://eng.umd.edu/∼blj/ papers/mobs2008.pdf
    • (2008) Proc. MOBS
    • Jaleel, A.1    Cohn, R.S.2    Luk, C.-K.3    Jacob, B.4
  • 27
    • 84881154274 scopus 로고    scopus 로고
    • ZSim: Fast and accurate microarchitectural simulation of thousand-core systems
    • Tel Aviv, Israel
    • D. Sanchez and C. Kozyrakis, "ZSim: Fast and accurate microarchitectural simulation of thousand-core systems," in Proc. ISCA, Tel Aviv, Israel, 2013, pp. 475-486.
    • (2013) Proc. ISCA , pp. 475-486
    • Sanchez, D.1    Kozyrakis, C.2
  • 28
    • 84892651281 scopus 로고    scopus 로고
    • QuickIA: Exploring heterogeneous architectures on real prototypes
    • New Orleans, LA, USA
    • N. Chitlur et al., "QuickIA: Exploring heterogeneous architectures on real prototypes," in Proc. HPCA, New Orleans, LA, USA, 2012, pp. 1-8.
    • (2012) Proc. HPCA , pp. 1-8
    • Chitlur, N.1
  • 29
    • 77953096885 scopus 로고    scopus 로고
    • PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
    • Dresden, Germany
    • J. Chan, G. Hendry, A. Biberman, K. Bergman, and L. P. Carloni, "PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks," in Proc. DATE, Dresden, Germany, 2010, pp. 691-696.
    • (2010) Proc. DATE , pp. 691-696
    • Chan, J.1    Hendry, G.2    Biberman, A.3    Bergman, K.4    Carloni, L.P.5
  • 31
    • 0033679915 scopus 로고    scopus 로고
    • Using complete system simulation for temporal debugging of general purpose operating systems and workload
    • San Francisco, CA, USA
    • L. Albertsson and P. S. Magnusson, "Using complete system simulation for temporal debugging of general purpose operating systems and workload," in Proc. MASCOTS, San Francisco, CA, USA, 2000, pp. 191-198.
    • (2000) Proc. MASCOTS , pp. 191-198
    • Albertsson, L.1    Magnusson, P.S.2
  • 32
    • 0038346244 scopus 로고    scopus 로고
    • SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling
    • San Diego, CA, USA
    • R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe, "SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling," in Proc. ISCA, San Diego, CA, USA, 2003, pp. 84-95.
    • (2003) Proc. ISCA , pp. 84-95
    • Wunderlich, R.E.1    Wenisch, T.F.2    Falsafi, B.3    Hoe, J.C.4
  • 33
    • 27544481926 scopus 로고    scopus 로고
    • Variability in architectural simulations of multi-threaded workloads
    • Anaheim, CA, USA
    • A. R. Alameldeen and D. A. Wood, "Variability in architectural simulations of multi-threaded workloads," in Proc. HPCA, Anaheim, CA, USA, 2003, pp. 7-18.
    • (2003) Proc. HPCA , pp. 7-18
    • Alameldeen, A.R.1    Wood, D.A.2
  • 34
    • 84963715919 scopus 로고    scopus 로고
    • Statistical performance comparisons of computers
    • New Orleans, LA, USA
    • T. Chen et al., "Statistical performance comparisons of computers," in Proc. HPCA, New Orleans, LA, USA, 2012, pp. 1-12.
    • (2012) Proc. HPCA , pp. 1-12
    • Chen, T.1
  • 36
    • 66749161432 scopus 로고    scopus 로고
    • Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach
    • Lake Como, Italy
    • R. Bitirgen, E. Ipek, and J. F. Martinez, "Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach," in Proc. MICRO, Lake Como, Italy, 2008, pp. 318-329.
    • (2008) Proc. MICRO , pp. 318-329
    • Bitirgen, R.1    Ipek, E.2    Martinez, J.F.3
  • 37
    • 70349185990 scopus 로고    scopus 로고
    • Machine learning based online performance prediction for runtime parallelization and task scheduling
    • Boston, MA, USA
    • J. Li et al., "Machine learning based online performance prediction for runtime parallelization and task scheduling," in Proc. ISPASS, Boston, MA, USA, 2009, pp. 89-100.
    • (2009) Proc. ISPASS , pp. 89-100
    • Li, J.1
  • 38
    • 79951697270 scopus 로고    scopus 로고
    • A predictive model for dynamic microarchitectural adaptivity control
    • Atlanta, GA, USA
    • C. Dubach, T. M. Jones, E. V. Bonilla, and M. F. P. O'Boyle, "A predictive model for dynamic microarchitectural adaptivity control," in Proc. MICRO, Atlanta, GA, USA, 2010, pp. 485-496.
    • (2010) Proc. MICRO , pp. 485-496
    • Dubach, C.1    Jones, T.M.2    Bonilla, E.V.3    O'Boyle, M.F.P.4
  • 39
    • 52649148744 scopus 로고    scopus 로고
    • Self-optimizing memory controllers: A reinforcement learning approach
    • Beijing, China
    • E. Ipek, O. Mutlu, J. F. Martinez, and R. Caruana, "Self-optimizing memory controllers: A reinforcement learning approach," in Proc. ISCA, Beijing, China, 2008, pp. 39-50.
    • (2008) Proc. ISCA , pp. 39-50
    • Ipek, E.1    Mutlu, O.2    Martinez, J.F.3    Caruana, R.4
  • 40
    • 85008031236 scopus 로고    scopus 로고
    • MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research
    • Jan./Dec.
    • A. J. KleinOsowski and D. J. Lilja, "MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research," Comput. Arch. Lett., vol. 1, no. 1, pp. 1-4, Jan./Dec. 2002.
    • (2002) Comput. Arch. Lett. , vol.1 , Issue.1 , pp. 1-4
    • KleinOsowski, A.J.1    Lilja, D.J.2
  • 41
    • 0037325558 scopus 로고    scopus 로고
    • Designing computer architecture research workloads
    • Feb.
    • L. Eeckhout, H. Vandierendonck, and K. De Bosschere, "Designing computer architecture research workloads," Computer, vol. 36, no. 2, pp. 65-71, Feb. 2003.
    • (2003) Computer , vol.36 , Issue.2 , pp. 65-71
    • Eeckhout, L.1    Vandierendonck, H.2    De Bosschere, K.3
  • 42
    • 84948454660 scopus 로고    scopus 로고
    • On the predictability of program behavior using different input data sets
    • Cambridge, MA, USA
    • W. C. Hsu, H. Chen, P. C. Yew, and H. Chen, "On the predictability of program behavior using different input data sets," in Proc. INTERACT, Cambridge, MA, USA, 2002, pp. 45-53.
    • (2002) Proc. INTERACT , pp. 45-53
    • Hsu, W.C.1    Chen, H.2    Yew, P.C.3    Chen, H.4
  • 43
    • 0035177240 scopus 로고    scopus 로고
    • Modeling superscalar processors via statistical simulation
    • Barcelona, Spain
    • S. Nussbaum and J. E. Smith, "Modeling superscalar processors via statistical simulation," in Proc. PACT, Barcelona, Spain, 2001, pp. 15-24.
    • (2001) Proc. PACT , pp. 15-24
    • Nussbaum, S.1    Smith, J.E.2
  • 44
    • 0242577987 scopus 로고    scopus 로고
    • Statistical simulation: Adding efficiency to the computer designer's toolbox
    • Sep./Oct.
    • L. Eeckhout, S. Nussbaum, J. E. Smith, and K. De Bosschere, "Statistical simulation: Adding efficiency to the computer designer's toolbox," IEEE Micro, vol. 23, no. 5, pp. 26-38, Sep./Oct. 2003.
    • (2003) IEEE Micro , vol.23 , Issue.5 , pp. 26-38
    • Eeckhout, L.1    Nussbaum, S.2    Smith, J.E.3    De Bosschere, K.4
  • 45
    • 0033719951 scopus 로고    scopus 로고
    • HLS: Combining statistical and symbolic simulation to guide microprocessor designs
    • Vancouver, BC, Canada
    • M. Oskin, F. T. Chong, and M. Farrens, "HLS: Combining statistical and symbolic simulation to guide microprocessor designs," in Proc. ISCA, Vancouver, BC, Canada, 2000, pp. 71-82.
    • (2000) Proc. ISCA , pp. 71-82
    • Oskin, M.1    Chong, F.T.2    Farrens, M.3
  • 46
    • 4644258856 scopus 로고    scopus 로고
    • Control flow modeling in statistical simulation for accurate and efficient processor design studies
    • Munchen, Germany, Jun.
    • L. Eeckhout, R. H. Bell, Jr., B. Stougie, K. De Bosschere, and L. K. John, "Control flow modeling in statistical simulation for accurate and efficient processor design studies," in Proc. ISCA, Munchen, Germany, Jun. 2004, pp. 350-361.
    • (2004) Proc. ISCA , pp. 350-361
    • Eeckhout, L.1    Bell, R.H.2    Stougie, B.3    De Bosschere, K.4    John, L.K.5
  • 47
    • 0009582811 scopus 로고    scopus 로고
    • Speculative updates of local and global branch history: A quantitative analysis
    • Jan.
    • K. Skadron, M. Martonosi, and D. W. Clark, "Speculative updates of local and global branch history: A quantitative analysis," J. Instr. Level Parallel., vol. 2, pp. 589-598, Jan. 2000.
    • (2000) J. Instr. Level Parallel. , vol.2 , pp. 589-598
    • Skadron, K.1    Martonosi, M.2    Clark, D.W.3
  • 48
    • 52949107219 scopus 로고    scopus 로고
    • Statistical simulation of chip multiprocessors running multi-program workloads
    • Lake Tahoe, CA, USA
    • D. Genbrugge and L. Eeckhout, "Statistical simulation of chip multiprocessors running multi-program workloads," in Proc. ICCD, Lake Tahoe, CA, USA, 2007, pp. 464-471.
    • (2007) Proc. ICCD , pp. 464-471
    • Genbrugge, D.1    Eeckhout, L.2
  • 49
    • 74549142310 scopus 로고    scopus 로고
    • Chip multiprocessor design space exploration through statistical simulation
    • Dec.
    • D. Genbrugge and L. Eeckhout, "Chip multiprocessor design space exploration through statistical simulation," IEEE Trans. Comput., vol. 58, no. 12, pp. 1668-1681, Dec. 2009.
    • (2009) IEEE Trans. Comput. , vol.58 , Issue.12 , pp. 1668-1681
    • Genbrugge, D.1    Eeckhout, L.2
  • 50
    • 56449115895 scopus 로고    scopus 로고
    • Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
    • Seattle, WA, USA
    • C. Hughes and T. Li, "Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis," in Proc. IISWC, Seattle, WA, USA, 2008, pp. 163-172.
    • (2008) Proc. IISWC , pp. 163-172
    • Hughes, C.1    Li, T.2
  • 51
    • 70349169075 scopus 로고    scopus 로고
    • Analyzing CUDA workloads using a detailed GPU simulator
    • Boston, MA, USA
    • A. Bakhoda, G. L. Yuan, W. W. L. Fung, H. Wong, and T. M. Aamodt, "Analyzing CUDA workloads using a detailed GPU simulator," in Proc. ISPASS, Boston, MA, USA, 2009, pp. 163-174.
    • (2009) Proc. ISPASS , pp. 163-174
    • Bakhoda, A.1    Yuan, G.L.2    Fung, W.W.L.3    Wong, H.4    Aamodt, T.M.5
  • 52
    • 84880232585 scopus 로고    scopus 로고
    • Accelerating GPGPU architecture simulation
    • Pittsburgh, PA, USA
    • Z. Yu et al., "Accelerating GPGPU architecture simulation," in Proc. SIGMETRICS, Pittsburgh, PA, USA, 2013, pp. 331-332.
    • (2013) Proc. SIGMETRICS , pp. 331-332
    • Yu, Z.1
  • 53
    • 0036953769 scopus 로고    scopus 로고
    • Automatically characterizing large scale program behavior
    • San Jose, CA, USA
    • T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, "Automatically characterizing large scale program behavior," in Proc. ASPLOS, San Jose, CA, USA, 2002, pp. 45-57.
    • (2002) Proc. ASPLOS , pp. 45-57
    • Sherwood, T.1    Perelman, E.2    Hamerly, G.3    Calder, B.4
  • 54
    • 0038345698 scopus 로고    scopus 로고
    • Phase tracking and prediction
    • San Diego, CA, USA
    • T. Sherwood, S. Sair, and B. Calder, "Phase tracking and prediction," in Proc. ISCA, San Diego, CA, USA, 2003, pp. 336-349.
    • (2003) Proc. ISCA , pp. 336-349
    • Sherwood, T.1    Sair, S.2    Calder, B.3
  • 56
    • 2642575180 scopus 로고    scopus 로고
    • A co-phase matrix to guide simultaneous multithreading simulation
    • Austin, TX, USA
    • M. Van Biesbrouck, T. Sherwood, and B. Calder, "A co-phase matrix to guide simultaneous multithreading simulation," in Proc. ISPASS, Austin, TX, USA, 2004, pp. 45-56.
    • (2004) Proc. ISPASS , pp. 45-56
    • Van Biesbrouck, M.1    Sherwood, T.2    Calder, B.3
  • 57
    • 21644454187 scopus 로고    scopus 로고
    • Pinpointing representative portions of large Intel Itanium programs with dynamic instrumentation
    • Portland, OR, USA
    • H. Patil et al., "Pinpointing representative portions of large Intel Itanium programs with dynamic instrumentation," in Proc. MICRO, Portland, OR, USA, 2004, pp. 81-92.
    • (2004) Proc. MICRO , pp. 81-92
    • Patil, H.1
  • 58
    • 84906709211 scopus 로고    scopus 로고
    • TBPoint: Reducing simulation time for large-scale GPGPU kernels
    • Phoenix, AZ, USA
    • J.-C. Huang, L. Nai, H. Kim, and H.-H. S. Lee, "TBPoint: Reducing simulation time for large-scale GPGPU kernels," in Proc. IPDPS, Phoenix, AZ, USA, 2014, pp. 437-446.
    • (2014) Proc. IPDPS , pp. 437-446
    • Huang, J.-C.1    Nai, L.2    Kim, H.3    Lee, H.-H.S.4
  • 59
    • 0030402384 scopus 로고    scopus 로고
    • Reducing state loss for effective trace sampling of superscalar processors
    • Austin, TX, USA
    • T. M. Conte, M. A. Hirsch, and K. N. Menezes, "Reducing state loss for effective trace sampling of superscalar processors," in Proc. ICCD, Austin, TX, USA, 1996, pp. 468-477.
    • (1996) Proc. ICCD , pp. 468-477
    • Conte, T.M.1    Hirsch, M.A.2    Menezes, K.N.3
  • 61
    • 33244477447 scopus 로고    scopus 로고
    • TurboSMARTS: Accurate microarchitecture simulation sampling in minutes
    • Banff, AB, Canada
    • T. F. Wenisch, R. E. Wunderlich, B. Falsafi, and J. C. Hoe, "TurboSMARTS: Accurate microarchitecture simulation sampling in minutes," in Proc. SIGMETRICS, Banff, AB, Canada, 2005, pp. 408-409.
    • (2005) Proc. SIGMETRICS , pp. 408-409
    • Wenisch, T.F.1    Wunderlich, R.E.2    Falsafi, B.3    Hoe, J.C.4
  • 62
    • 27544466004 scopus 로고    scopus 로고
    • SimFlex: A fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture
    • N. Hardavellas et al., "SimFlex: A fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture," SIGMETRICS Perform. Eval. Rev., vol. 31, no. 4, pp. 31-35, 2004.
    • (2004) SIGMETRICS Perform. Eval. Rev. , vol.31 , Issue.4 , pp. 31-35
    • Hardavellas, N.1
  • 63
    • 33748289310 scopus 로고    scopus 로고
    • SimFlex: Statistical sampling of computer system simulation
    • Jul./Aug.
    • T. F. Wenisch et al., "SimFlex: Statistical sampling of computer system simulation," IEEE Micro, vol. 26, no. 4, pp. 18-31, Jul./Aug. 2006.
    • (2006) IEEE Micro , vol.26 , Issue.4 , pp. 18-31
    • Wenisch, T.F.1
  • 64
    • 84880272089 scopus 로고    scopus 로고
    • ESESC: A fast multicore simulator using time-based sampling
    • Shenzhen, China
    • E. K. Ardestani and J. Renau, "ESESC: A fast multicore simulator using time-based sampling," in Proc. HPCA, Shenzhen, China, 2013, pp. 448-459.
    • (2013) Proc. HPCA , pp. 448-459
    • Ardestani, E.K.1    Renau, J.2
  • 65
    • 84881442631 scopus 로고    scopus 로고
    • Sampled simulation of multi-threaded applications
    • Austin, TX, USA
    • T. E. Carlson, W. Heirman, and L. Eeckhout, "Sampled simulation of multi-threaded applications," in Proc. ISPASS, Austin, TX, USA, 2013, pp. 2-12.
    • (2013) Proc. ISPASS , pp. 2-12
    • Carlson, T.E.1    Heirman, W.2    Eeckhout, L.3
  • 66
    • 84904497940 scopus 로고    scopus 로고
    • BarrierPoint: Sampled simulation of multi-threaded applications
    • Monterey, CA, USA
    • T. E. Carlson, W. Heirman, K. Van Craeynest, and L. Eeckhout, "BarrierPoint: Sampled simulation of multi-threaded applications," in Proc. ISPASS, Monterey, CA, USA, 2014, pp. 2-12.
    • (2014) Proc. ISPASS , pp. 2-12
    • Carlson, T.E.1    Heirman, W.2    Van Craeynest, K.3    Eeckhout, L.4
  • 67
    • 84948749348 scopus 로고    scopus 로고
    • Workload design: Selecting representative program-input pairs
    • Charlottesville, VA, USA
    • L. Eeckhout, H. Vandierendonck, and K. De Bosschere, "Workload design: Selecting representative program-input pairs," in Proc. PACT, Charlottesville, VA, USA, 2002, pp. 83-94.
    • (2002) Proc. PACT , pp. 83-94
    • Eeckhout, L.1    Vandierendonck, H.2    De Bosschere, K.3
  • 68
    • 33749073811 scopus 로고    scopus 로고
    • Exploiting program microarchitecture independent characteristics and phase behavior for reduced benchmark suite simulation
    • Austin, TX, USA
    • L. Eeckhout, J. Sampson, and B. Calder, "Exploiting program microarchitecture independent characteristics and phase behavior for reduced benchmark suite simulation," in Proc. IISWC, Austin, TX, USA, 2005, pp. 2-12.
    • (2005) Proc. IISWC , pp. 2-12
    • Eeckhout, L.1    Sampson, J.2    Calder, B.3
  • 69
    • 33646486530 scopus 로고    scopus 로고
    • Measuring benchmark similarity using inherent program characteristics
    • Jun.
    • A. Joshi, A. Phansalkar, L. Eeckhout, and L. K. John, "Measuring benchmark similarity using inherent program characteristics," IEEE Trans. Comput., vol. 55, no. 6, pp. 769-782, Jun. 2006.
    • (2006) IEEE Trans. Comput. , vol.55 , Issue.6 , pp. 769-782
    • Joshi, A.1    Phansalkar, A.2    Eeckhout, L.3    John, L.K.4
  • 70
    • 34247169237 scopus 로고    scopus 로고
    • Performance prediction based on inherent program similarity
    • San Francisco, CA, USA
    • K. Hoste et al., "Performance prediction based on inherent program similarity," in Proc. PACT, San Francisco, CA, USA, 2006, pp. 114-122.
    • (2006) Proc. PACT , pp. 114-122
    • Hoste, K.1
  • 71
    • 77952283142 scopus 로고    scopus 로고
    • HASS: A scheduler for heterogeneous multicore systems
    • D. Shelepov et al., "HASS: A scheduler for heterogeneous multicore systems," ACM SIGOPS Oper. Syst. Rev., vol. 43, no. 2, pp. 66-75, 2009.
    • (2009) ACM SIGOPS Oper. Syst. Rev. , vol.43 , Issue.2 , pp. 66-75
    • Shelepov, D.1
  • 72
    • 77954693412 scopus 로고    scopus 로고
    • Evaluating iterative optimization across 1000 datasets
    • Toronto, ON, Canada
    • Y. Chen et al., "Evaluating iterative optimization across 1000 datasets," in Proc. PLDI, Toronto, ON, Canada, 2010, pp. 448-459.
    • (2010) Proc. PLDI , pp. 448-459
    • Chen, Y.1
  • 73
    • 33749057743 scopus 로고    scopus 로고
    • A statistically rigorous approach for improving simulation methodology
    • Anaheim, CA, USA
    • J. J. Yi, D. J. Lilja, and D. M. Hawkins, "A statistically rigorous approach for improving simulation methodology," in Proc. HPCA, Anaheim, CA, USA, 2003, pp. 281-291.
    • (2003) Proc. HPCA , pp. 281-291
    • Yi, J.J.1    Lilja, D.J.2    Hawkins, D.M.3
  • 74
    • 52249100002 scopus 로고    scopus 로고
    • Subsetting the SPEC CPU2006 benchmark suite
    • A. Phansalkar, A. Joshi, and L. K. John, "Subsetting the SPEC CPU2006 benchmark suite," SIGARCH Comput. Archit. News, vol. 35, no. 1, pp. 69-76, 2007.
    • (2007) SIGARCH Comput. Archit. News , vol.35 , Issue.1 , pp. 69-76
    • Phansalkar, A.1    Joshi, A.2    John, L.K.3
  • 75
    • 35348913704 scopus 로고    scopus 로고
    • Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
    • San Diego, CA, USA
    • A. Phansalkar, A. Joshi, and L. K. John, "Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite," in Proc. ISCA, San Diego, CA, USA, 2007, pp. 412-423.
    • (2007) Proc. ISCA , pp. 412-423
    • Phansalkar, A.1    Joshi, A.2    John, L.K.3
  • 76
    • 51549090235 scopus 로고    scopus 로고
    • Improve simulation efficiency using statistical benchmark subsetting: An implantBench case study
    • Anaheim, CA, USA
    • Z. Jin and A. C. Cheng, "Improve simulation efficiency using statistical benchmark subsetting: An implantBench case study," in Proc. DAC, Anaheim, CA, USA, 2008, pp. 970-973.
    • (2008) Proc. DAC , pp. 970-973
    • Jin, Z.1    Cheng, A.C.2
  • 77
    • 85008006298 scopus 로고    scopus 로고
    • Evolutionary benchmark subsetting
    • Nov./Dec.
    • Z. Jin and A. C. Cheng, "Evolutionary benchmark subsetting," IEEE Micro, vol. 28, no. 6, pp. 20-36, Nov./Dec. 2008.
    • (2008) IEEE Micro , vol.28 , Issue.6 , pp. 20-36
    • Jin, Z.1    Cheng, A.C.2
  • 78
    • 79952550796 scopus 로고    scopus 로고
    • SubsetTrio: An evolutionary, geometric, and statistical benchmark subsetting framework
    • Z. Jin and A. C. Cheng, "SubsetTrio: An evolutionary, geometric, and statistical benchmark subsetting framework," ACM Trans. Model. Comput. Simulat., vol. 21, no. 3, pp. 1-23, 2011.
    • (2011) ACM Trans. Model. Comput. Simulat. , vol.21 , Issue.3 , pp. 1-23
    • Jin, Z.1    Cheng, A.C.2
  • 79
    • 33748863916 scopus 로고    scopus 로고
    • Construction and use of linear regression models for processor performance analysis
    • Austin, TX, USA
    • P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil, "Construction and use of linear regression models for processor performance analysis," in Proc. HPCA, Austin, TX, USA, 2006, pp. 99-108.
    • (2006) Proc. HPCA , pp. 99-108
    • Joseph, P.J.1    Vaswani, K.2    Thazhuthaveetil, M.J.3
  • 80
    • 34548333834 scopus 로고    scopus 로고
    • A predictive performance model for superscalar processors
    • Orlando, FL, USA
    • P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil, "A predictive performance model for superscalar processors," in Proc. MICRO, Orlando, FL, USA, 2006, pp. 161-170.
    • (2006) Proc. MICRO , pp. 161-170
    • Joseph, P.J.1    Vaswani, K.2    Thazhuthaveetil, M.J.3
  • 81
    • 34547288276 scopus 로고    scopus 로고
    • Accurate and efficient regression modeling for microarchitectural performance and power prediction
    • San Jose, CA, USA
    • B. C. Lee and D. M. Brooks, "Accurate and efficient regression modeling for microarchitectural performance and power prediction," in Proc. ASPLOS, San Jose, CA, USA, 2006, pp. 185-194.
    • (2006) Proc. ASPLOS , pp. 185-194
    • Lee, B.C.1    Brooks, D.M.2
  • 82
    • 34547702258 scopus 로고    scopus 로고
    • Illustrative design space studies with microarchitectural regression models
    • Scottsdale, AZ, USA
    • B. C. Lee and D. M. Brooks, "Illustrative design space studies with microarchitectural regression models," in Proc. HPCA, Scottsdale, AZ, USA, 2007, pp. 340-351.
    • (2007) Proc. HPCA , pp. 340-351
    • Lee, B.C.1    Brooks, D.M.2
  • 83
    • 77958078100 scopus 로고    scopus 로고
    • Applied inference: Case studies in microarchitectural design
    • B. C. Lee and D. Brooks, "Applied inference: Case studies in microarchitectural design," ACM Trans. Archit. Code Optim., vol. 7, no. 2, pp. 1-37, 2010.
    • (2010) ACM Trans. Archit. Code Optim. , vol.7 , Issue.2 , pp. 1-37
    • Lee, B.C.1    Brooks, D.2
  • 84
    • 84876529275 scopus 로고    scopus 로고
    • Inferred models for dynamic and sparse hardware-software spaces
    • Vancouver, BC, Canada
    • W. Wu and B. C. Lee, "Inferred models for dynamic and sparse hardware-software spaces," in Proc. MICRO, Vancouver, BC, Canada, 2012, pp. 413-424.
    • (2012) Proc. MICRO , pp. 413-424
    • Wu, W.1    Lee, B.C.2
  • 85
    • 66749185800 scopus 로고    scopus 로고
    • CPR: Composable performance regression for scalable multiprocessor models
    • Lake Como, Italy
    • B. C. Lee, J. Collins, H. Wang, and D. Brooks, "CPR: Composable performance regression for scalable multiprocessor models," in Proc. MICRO, Lake Como, Italy, 2008, pp. 270-281.
    • (2008) Proc. MICRO , pp. 270-281
    • Lee, B.C.1    Collins, J.2    Wang, H.3    Brooks, D.4
  • 86
    • 34547417098 scopus 로고    scopus 로고
    • Efficiently exploring architectural design spaces via predictive modeling
    • San Jose, CA, USA
    • E. Ïpek, S. A. McKee, R. Caruana, B. R. De Supinski, and M. Schulz, "Efficiently exploring architectural design spaces via predictive modeling," in Proc. ASPLOS, San Jose, CA, USA, 2006, pp. 195-206.
    • (2006) Proc. ASPLOS , pp. 195-206
    • Ïpek, E.1    McKee, S.A.2    Caruana, R.3    De Supinski BRSchulz, M.4
  • 87
    • 66749097272 scopus 로고    scopus 로고
    • Efficient architectural design space exploration via predictive modeling
    • E. Ipek et al., "Efficient architectural design space exploration via predictive modeling," ACM Trans. Archit. Code Optim., vol. 4, no. 4, pp. 1-34, 2008.
    • (2008) ACM Trans. Archit. Code Optim. , vol.4 , Issue.4 , pp. 1-34
    • Ipek, E.1
  • 88
    • 47349128440 scopus 로고    scopus 로고
    • Informed microarchitecture design space exploration using workload dynamics
    • Chicago, IL, USA
    • C.-B. Cho, W. Zhang, and T. Li, "Informed microarchitecture design space exploration using workload dynamics," in Proc. MICRO, Chicago, IL, USA, 2007, pp. 274-285.
    • (2007) Proc. MICRO , pp. 274-285
    • Cho, C.-B.1    Zhang, W.2    Li, T.3
  • 89
    • 51549114087 scopus 로고    scopus 로고
    • Predictive design space exploration using genetically programmed response surfaces
    • Anaheim, CA, USA
    • H. Cook and K. Skadron, "Predictive design space exploration using genetically programmed response surfaces," in Proc. DAC, Anaheim, CA, USA, 2008, pp. 960-965.
    • (2008) Proc. DAC , pp. 960-965
    • Cook, H.1    Skadron, K.2
  • 90
    • 70450247054 scopus 로고    scopus 로고
    • ReSPIR: A response surface-based Pareto iterative refinement for application-specific design space exploration
    • Dec.
    • G. Palermo, C. Silvano, and V. Zaccaria, "ReSPIR: A response surface-based Pareto iterative refinement for application-specific design space exploration," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 12, pp. 1816-1829, Dec. 2009.
    • (2009) IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. , vol.28 , Issue.12 , pp. 1816-1829
    • Palermo, G.1    Silvano, C.2    Zaccaria, V.3
  • 91
    • 84881073232 scopus 로고    scopus 로고
    • Effective and efficient microprocessor design space exploration using unlabeled design configurations
    • Barcelona, Spain
    • Q. Guo et al., "Effective and efficient microprocessor design space exploration using unlabeled design configurations," in Proc. IJCAI, Barcelona, Spain, 2011, pp. 1671-1677.
    • (2011) Proc. IJCAI , pp. 1671-1677
    • Guo, Q.1
  • 92
    • 84891783012 scopus 로고    scopus 로고
    • Effective and efficient microprocessor design space exploration using unlabeled design configurations
    • T. Chen et al., "Effective and efficient microprocessor design space exploration using unlabeled design configurations," ACM Trans. Intell. Syst. Technol., vol. 5, no. 1, pp. 20:1-20:18, 2013.
    • (2013) ACM Trans. Intell. Syst. Technol. , vol.5 , Issue.1 , pp. 201-2018
    • Chen, T.1
  • 93
    • 84905495779 scopus 로고    scopus 로고
    • ArchRanker: A ranking approach to design space exploration
    • Minneapolis, MN, USA
    • T. Chen et al., "ArchRanker: A ranking approach to design space exploration," in Proc. ISCA, Minneapolis, MN, USA, 2014, pp. 85-96.
    • (2014) Proc. ISCA , pp. 85-96
    • Chen, T.1
  • 94
    • 84897903769 scopus 로고    scopus 로고
    • DRuiD: Designing reconfigurable architectures with decision-making support
    • Singapore
    • G. Mariani et al., "DRuiD: Designing reconfigurable architectures with decision-making support," in Proc. ASP-DAC, Singapore, 2014, pp. 213-218.
    • (2014) Proc. ASP-DAC , pp. 213-218
    • Mariani, G.1
  • 95
    • 34547174070 scopus 로고    scopus 로고
    • Multi-objective design space exploration of embedded systems
    • G. Palermo, C. Silvano, and V. Zaccaria, "Multi-objective design space exploration of embedded systems," J. Embedded Comput., vol. 1, no. 3, pp. 305-316, 2005.
    • (2005) J. Embedded Comput. , vol.1 , Issue.3 , pp. 305-316
    • Palermo, G.1    Silvano, C.2    Zaccaria, V.3
  • 96
    • 34248506586 scopus 로고    scopus 로고
    • Efficient design space exploration for application specific systems-on-a-chip
    • G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, and D. Patti, "Efficient design space exploration for application specific systems-on-a-chip," J. Syst. Archit., vol. 53, no. 10, pp. 733-750, 2007.
    • (2007) J. Syst. Archit. , vol.53 , Issue.10 , pp. 733-750
    • Ascia, G.1    Catania, V.2    Di Nuovo, A.G.3    Palesi, M.4    Patti, D.5
  • 97
    • 77956212269 scopus 로고    scopus 로고
    • A correlation-based design space exploration methodology for multi-processor systems-on-chip
    • Anaheim, CA, USA
    • G. Mariani et al., "A correlation-based design space exploration methodology for multi-processor systems-on-chip," in Proc. DAC, Anaheim, CA, USA, 2010, pp. 120-125.
    • (2010) Proc. DAC , pp. 120-125
    • Mariani, G.1
  • 98
    • 0036530772 scopus 로고    scopus 로고
    • A fast and elitist multiobjective genetic algorithm: NSGA-II
    • Apr.
    • K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: NSGA-II," IEEE Trans. Evol. Comput., vol. 6, no. 2, pp. 182-197, Apr. 2002.
    • (2002) IEEE Trans. Evol. Comput. , vol.6 , Issue.2 , pp. 182-197
    • Deb, K.1    Pratap, A.2    Agarwal, S.3    Meyarivan, T.4
  • 99
    • 84921448683 scopus 로고    scopus 로고
    • DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling
    • Feb.
    • G. Mariani, G. Palermo, V. Zaccaria, and C. Silvano, "DeSpErate++: An enhanced design space exploration framework using predictive simulation scheduling," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 34, no. 2, pp. 293-306, Feb. 2015.
    • (2015) IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. , vol.34 , Issue.2 , pp. 293-306
    • Mariani, G.1    Palermo, G.2    Zaccaria, V.3    Silvano, C.4
  • 100
    • 4644299010 scopus 로고    scopus 로고
    • A first-order superscalar processor model
    • Munich, Germany
    • T. S. Karkhanis and J. E. Smith, "A first-order superscalar processor model," in Proc. ISCA, Munich, Germany, 2004, pp. 338-349.
    • (2004) Proc. ISCA , pp. 338-349
    • Karkhanis, T.S.1    Smith, J.E.2
  • 101
    • 34249813667 scopus 로고    scopus 로고
    • A performance counter architecture for computing accurate CPI components
    • San Jose, CA, USA
    • S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith, "A performance counter architecture for computing accurate CPI components," in Proc. ASPLOS, San Jose, CA, USA, 2006, pp. 175-184.
    • (2006) Proc. ASPLOS , pp. 175-184
    • Eyerman, S.1    Eeckhout, L.2    Karkhanis, T.3    Smith, J.E.4
  • 102
    • 67650312346 scopus 로고    scopus 로고
    • A mechanistic performance model for superscalar out-of-order processors
    • S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith, "A mechanistic performance model for superscalar out-of-order processors," ACM Trans. Comput. Syst., vol. 27, no. 2, pp. 1-37, 2009.
    • (2009) ACM Trans. Comput. Syst. , vol.27 , Issue.2 , pp. 1-37
    • Eyerman, S.1    Eeckhout, L.2    Karkhanis, T.3    Smith, J.E.4
  • 103
    • 79961189225 scopus 로고    scopus 로고
    • How sensitive is processor customization to the workload's input datasets?
    • San Diego, CA, USA
    • M. Breughe et al., "How sensitive is processor customization to the workload's input datasets?" in Proc. ASAP, San Diego, CA, USA, 2011, pp. 1-7.
    • (2011) Proc. ASAP , pp. 1-7
    • Breughe, M.1
  • 104
    • 84921293471 scopus 로고    scopus 로고
    • Mechanistic analytical modeling of superscalar in-order processor performance
    • M. B. Breughe, S. Eyerman, and L. Eeckhout, "Mechanistic analytical modeling of superscalar in-order processor performance," ACM Trans. Archit. Code Optim., vol. 11, no. 4, pp. 1-26, 2015.
    • (2015) ACM Trans. Archit. Code Optim. , vol.11 , Issue.4 , pp. 1-26
    • Breughe, M.B.1    Eyerman, S.2    Eeckhout, L.3
  • 105
    • 84937468659 scopus 로고    scopus 로고
    • Micro-architecture independent analytical performance and power modeling
    • Philadelphia, PA, USA
    • S. Van den Steen et al., "Micro-architecture independent analytical performance and power modeling," in Proc. ISPASS, Philadelphia, PA, USA, 2015, pp. 32-41.
    • (2015) Proc. ISPASS , pp. 32-41
    • Van den Steen, S.1
  • 106
    • 0037325540 scopus 로고    scopus 로고
    • Queuing simulation model for multiprocessor systems
    • Feb.
    • T.-F. Tsuei and W. Yamamoto, "Queuing simulation model for multiprocessor systems," Computer, vol. 36, no. 2, pp. 58-64, Feb. 2003.
    • (2003) Computer , vol.36 , Issue.2 , pp. 58-64
    • Tsuei, T.-F.1    Yamamoto, W.2
  • 107
    • 47349128966 scopus 로고    scopus 로고
    • Microarchitectural design space exploration using an architecture-centric approach
    • Chicago, IL, USA
    • C. Dubach, T. M. Jones, and M. F. P. O'Boyle, "Microarchitectural design space exploration using an architecture-centric approach," in Proc. MICRO, Chicago, IL, USA, 2007, pp. 262-271.
    • (2007) Proc. MICRO , pp. 262-271
    • Dubach, C.1    Jones, T.M.2    O'Boyle, M.F.P.3
  • 108
    • 47849123249 scopus 로고    scopus 로고
    • Using predic-tivemodeling for cross-program design space exploration in multicore systems
    • Brasov, Romania
    • S. Khan, P. Xekalakis, J. Cavazos, and M. Cintra, "Using predic-tivemodeling for cross-program design space exploration in multicore systems," in Proc. PACT, Brasov, Romania, 2007, pp. 327-338.
    • (2007) Proc. PACT , pp. 327-338
    • Khan, S.1    Xekalakis, P.2    Cavazos, J.3    Cintra, M.4
  • 109
    • 63349088199 scopus 로고    scopus 로고
    • Exploring and predicting the architecture/optimising compiler co-design space
    • Atlanta, GA, USA
    • C. Dubach, T. M. Jones, and M. F. P. O'Boyle, "Exploring and predicting the architecture/optimising compiler co-design space," in Proc. CASES, Atlanta, GA, USA, 2008, pp. 31-40.
    • (2008) Proc. CASES , pp. 31-40
    • Dubach, C.1    Jones, T.M.2    O'Boyle, M.F.P.3
  • 110
    • 77954986440 scopus 로고    scopus 로고
    • Energy-performance tradeoffs in processor architecture and circuit design: A marginal cost analysis
    • Saint-Malo, France
    • O. Azizi, A. Mahesri, B. C. Lee, S. J. Patel, and M. Horowitz, "Energy-performance tradeoffs in processor architecture and circuit design: A marginal cost analysis," in Proc. ISCA, Saint-Malo, France, 2010, pp. 26-36.
    • (2010) Proc. ISCA , pp. 26-36
    • Azizi, O.1    Mahesri, A.2    Lee, B.C.3    Patel, S.J.4    Horowitz, M.5
  • 111
    • 79955430619 scopus 로고    scopus 로고
    • IBM power edge of network processor: A wire-speed system on a chip
    • Mar./Apr.
    • J. D. Brown, S. Woodward, B. M. Bass, and C. L. Johnson, "IBM power edge of network processor: A wire-speed system on a chip," IEEE Micro, vol. 31, no. 2, pp. 76-85, Mar./Apr. 2011.
    • (2011) IEEE Micro , vol.31 , Issue.2 , pp. 76-85
    • Brown, J.D.1    Woodward, S.2    Bass, B.M.3    Johnson, C.L.4
  • 112
    • 84872103675 scopus 로고    scopus 로고
    • T4: A highly threaded server-on-a-chip with native support for heterogeneous computing
    • [Online]
    • R. Golla and P. Jordan, "T4: A highly threaded server-on-a-chip with native support for heterogeneous computing," in Proc. Hot Chip Symp., 2011. [Online]. Available: http://www.hotchips.org/ wp-content/uploads/hc-archives/hc23/HC23.19.7-Server/HC23.19.731-T4-Golla-Oracle-hotchips-corrected.pdf
    • (2011) Proc. Hot Chip Symp.
    • Golla, R.1    Jordan, P.2
  • 113
    • 77952256041 scopus 로고    scopus 로고
    • Conservation cores: Reducing the energy of mature computations
    • Pittsburgh, PA, USA
    • G. Venkatesh et al., "Conservation cores: Reducing the energy of mature computations," in Proc. ASPLOS, Pittsburgh, PA, USA, 2010, pp. 205-218.
    • (2010) Proc. ASPLOS , pp. 205-218
    • Venkatesh, G.1
  • 114
    • 84863543742 scopus 로고    scopus 로고
    • Architecture support for accelerator-rich CMPs
    • San Francisco, CA, USA
    • J. Cong, M. A. Ghodrat, M. Gill, B. Grigorian, and G. Reinman, "Architecture support for accelerator-rich CMPs," in Proc. DAC, San Francisco, CA, USA, 2012, pp. 843-849.
    • (2012) Proc. DAC , pp. 843-849
    • Cong, J.1    Ghodrat, M.A.2    Gill, M.3    Grigorian, B.4    Reinman, G.5
  • 115
    • 79953076698 scopus 로고    scopus 로고
    • High-level synthesis for FPGAs: From prototyping to deployment
    • Apr.
    • J. Cong et al., "High-level synthesis for FPGAs: From prototyping to deployment," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 4, pp. 473-491, Apr. 2011.
    • (2011) IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. , vol.30 , Issue.4 , pp. 473-491
    • Cong, J.1
  • 116
    • 19344368072 scopus 로고    scopus 로고
    • Spiral: Code generation for DSP transforms
    • Feb.
    • M. Puschel et al., "Spiral: Code generation for DSP transforms," Proc. IEEE, vol. 93, no. 2, pp. 232-275, Feb. 2005.
    • (2005) Proc. IEEE , vol.93 , Issue.2 , pp. 232-275
    • Puschel, M.1
  • 117
    • 84881144734 scopus 로고    scopus 로고
    • Thin servers with smart pipes: Designing SoC accelerators for mem-cached
    • Tel Aviv, Israel
    • K. Lim, D. Meisner, A. G. Saidi, P. Ranganathan, and T. F. Wenisch, "Thin servers with smart pipes: Designing SoC accelerators for mem-cached," in Proc. ISCA, Tel Aviv, Israel, 2013, pp. 36-47.
    • (2013) Proc. ISCA , pp. 36-47
    • Lim, K.1    Meisner, D.2    Saidi, A.G.3    Ranganathan, P.4    Wenisch, T.F.5
  • 118
    • 84897819422 scopus 로고    scopus 로고
    • Q100: The architecture and design of a database processing unit
    • Salt Lake City, UT, USA
    • L. Wu, A. Lottarini, T. K. Paine, M. A. Kim, and K. A. Ross, "Q100: The architecture and design of a database processing unit," in Proc. ASPLOS, Salt Lake City, UT, USA, 2014, pp. 255-268.
    • (2014) Proc. ASPLOS , pp. 255-268
    • Wu, L.1    Lottarini, A.2    Paine, T.K.3    Kim, M.A.4    Ross, K.A.5
  • 119
    • 79955370378 scopus 로고    scopus 로고
    • The future of microprocessors
    • S. Borkar and A. A. Chien, "The future of microprocessors," ACM Commun., vol. 54, no. 5, pp. 67-77, 2011.
    • (2011) ACM Commun. , vol.54 , Issue.5 , pp. 67-77
    • Borkar, S.1    Chien, A.A.2
  • 120
    • 84898887257 scopus 로고    scopus 로고
    • Systematic evaluation of workload clustering for extremely energy-efficient architectures
    • A. Guha, Y. Zhang, R. Ur Rasool, and A. A. Chien, "Systematic evaluation of workload clustering for extremely energy-efficient architectures," ACM SIGARCH Comput. Archit. News, vol. 41, no. 2, pp. 22-29, 2013.
    • (2013) ACM SIGARCH Comput. Archit. News , vol.41 , Issue.2 , pp. 22-29
    • Guha, A.1    Zhang, Y.2    Ur Rasool, R.3    Chien, A.A.4
  • 121
    • 84906342287 scopus 로고    scopus 로고
    • Understanding the design space of DRAM-optimized hardware FFT accelerators
    • Zurich, Switzerland
    • B. Akin, F. Franchetti, and J. C. Hoe, "Understanding the design space of DRAM-optimized hardware FFT accelerators," in Proc. ASAP, Zurich, Switzerland, 2014, pp. 248-255.
    • (2014) Proc. ASAP , pp. 248-255
    • Akin, B.1    Franchetti, F.2    Hoe, J.C.3
  • 122
    • 84905487457 scopus 로고    scopus 로고
    • Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
    • Minneapolis, MN, USA
    • Y. S. Shao, B. Reagen, G.-Y. Wei, and D. Brooks, "Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures," in Proc. ISCA, Minneapolis, MN, USA, 2014, pp. 97-108.
    • (2014) Proc. ISCA , pp. 97-108
    • Shao, Y.S.1    Reagen, B.2    Wei, G.-Y.3    Brooks, D.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.