A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 59, Issue , 2016, Pages 316-317

  Sohn, Kyomin ^a   Yun, Won Joo ^a   Oh, Reum ^a   Oh, Chi Sung ^a   Seo, Seong Young ^a   Park, Min Sang ^a   Shin, Dong Hak ^a   Jung, Won Chang ^a   Shin, Sang Hoon ^a   Ryu, Je Min ^a   Yu, Hye Seung ^a   Jung, Jae Hun ^a   Nam, Kyung Woo ^a   Choi, Seouk Kyu ^a   Lee, Jae Wook ^a   Kang, Uksong ^a   Sohn, Young Soo ^a   Choi, Jung Hwan ^a   Kim, Chi Wook ^a   Jang, Seong Jin ^a   Jin, Gyo Young ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUITS; POLYCHLORINATED BIPHENYLS; RECONFIGURABLE HARDWARE; TEMPERATURE DISTRIBUTION; THREE DIMENSIONAL INTEGRATED CIRCUITS;

BANDWIDTH LIMITEDS; GRAPHICS APPLICATIONS; HIGH BANDWIDTH; HIGH PERFORMANCE COMPUTING; HIGH POWER CONSUMPTION; ROUTING CONGESTION; STACK CONFIGURATIONS; THERMAL SOLUTION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84962878072     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2016.7418034     Document Type: Conference Paper

References (3)

1. D. U. Lee, et al., "A 1. 2V 8Gb 8-Channel 128GB/s High-Bandwidth Memory (HBM) Stacked DRAM with Effective Microbump I/O Test Methods Using 29nm Process and TSV, " ISSCC Dig. Tech. Papers, pp. 432-433, Feb. 2014.
2. "High Bandwidth Memory (HBM) DRAM Specification, " JEDEC Standard, Oct 2013.
3. D. U. Lee, et al., "An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory (HBM) stacked DRAM, " IEEE Symp. VLSI Circuits, pp. 1-2, June 2015.