A system level approach in designing dual-duplex fault tolerant embedded systems

Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002

Volumn , Issue , 2002, Pages 32-36

  Bolchini, C ^a   Pomante, L ^a   Salice, F ^a   Sciuto, D ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; ELECTRIC POWER UTILIZATION; FAULT TOLERANCE; HARDWARE; HARDWARE-SOFTWARE CODESIGN; RECONFIGURABLE HARDWARE; REDUNDANCY; RELIABILITY;

FAULT TOLERANCE PROPERTY; HW/SW PARTITIONING; REFERENCE SYSTEMS; RELIABILITY CONSTRAINTS; RELIABILITY METHODOLOGY; RELIABLE EMBEDDED SYSTEMS; SPECIFIC HARDWARE; SYSTEM-LEVEL APPROACH;

EMBEDDED SYSTEMS;

EID: 84962747763     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2002.1030180     Document Type: Conference Paper

References (12)

1. L. Pomante, "System Level Concurrent Error Detection," Tech. Rep. RT-00003. Cefriel-Politecnico di Milano, Milano.
2. M. Blum, H. Wasserman, "Reflections on the Pentium division bug," IEEE Trans. on Computers, Vol.: 45, no. 4, April 1996, pp. 385-393.
3. D.C. Shreve, D.J. Mellema, C.B. Boettcher, "Real-time checkers: built-in-test for mission-critical software," AIAA/IEEE 16th Digital Avionics Systems Conf., 1997, vol. 1, pp. 1.4-1.8.
4. H. Wasserman, M. Blum, "Software reliability via run-time result checking," Journal of the ACM, 44(6): 826-849, Nov. 1997.
5. Z. Alkhalifa, V. S. S. Nair, J. A. Abraham, "Design and evaluation of system-level checks for on-line control flow error detection," IEEE Trans. Parallel and Distributed System, vol. 10, no. 6, June 1999, pp. 627-641.
6. G.A. Kanawati, V.S.S. Nair, N. Krishnamurthy, J.A. Abraham, "Evaluation of integrated system-level checks for on-line error detection," Proc. IEEE Int. Computer Performance and Dependability Symp., 1996, pp. 92-301.
7. F. Rashid, K. K. Saluja, P. Ramanathan, "Fault tolerance through re-execution in multiscalar architecture", Proc. Int. Conference on Dependable Systems and Networks (DNS 2000), 482-491, 2000.
8. C. Wah, A. Orailoglu, "High-level synthesis of gracefully degradable ASICs," Proc. European Design and Test Conference, 1996. (ED&TC'96), pp. 50-54, 1996.
9. D. K. Pradhan, editor. Fault Tolerant computing, Theory and Techniques, Vol. 1, Prentice Hall, Englewood Cliffs, NJ, U.S.A., 1986.
10. C. Bolchini, R. Montandon, F. Salice, D. Sciuto, "Design of VHDL based Totally Self-Checking Finite State machine and Data Path descriptions", IEEE Trans. on VLSI Systems, vol. 8, n. 1, Feb. 2000, pp. 82-102.
11. C. Bolchini, L. Pomante, F. Salice and D. Sciuto, "On-Line Fault Detection in a Hardware/Software Co-Design Environment: System Partitioning" Proc. IEEE/ACM Int. Symp. System Synthesis, Montreal, Ca., 2001, pp. 51-56.
12. C. Bolchini, F. Salice "A Software Methodology For Detecting Hardware Faults in VLIW Data Paths", Proc. IEEE DFT Symp., San Francisco, USA, October 2001, pp.170-175.