Examining performance differences in workload execution phases

2001 IEEE International Workshop on Workload Characterization, WWC 2001

Volumn , Issue , 2001, Pages 82-90

  Cook, J ^a   Oliver, R L ^a   Johnson, E E ^a  

^a NEW MEXICO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION;

ARBITRARY NUMBER; BEHAVIORAL CHARACTERISTICS; BENCHMARK SUITES; EXECUTED INSTRUCTIONS; EXECUTION PHASIS; PERFORMANCE ANALYSIS; WORKLOAD CHARACTERIZATION; WORKLOAD EXECUTION;

COMPUTER ARCHITECTURE;

EID: 84962701674     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WWC.2001.990747     Document Type: Conference Paper

References (17)

1. A. Borg, R. E. Kessler, and D. W. Wall. Generation and Analysis of Very Long Address Traces. In The 17th Annual Symposium on Computer Architecture, pages 270-279, 1990.
2. P. Bose and T. M. Conte. Performance Analysis and Its Impact on Design. Computer, 31(5):41-49, May 1998.
3. J. P. Bradford and J. Fortes. Performance and Memory-Access Characterization of Data Mining Applications. In L. John and A. M. G. Maynard, editors, Workload Characterization: Methodology and Case Studies. IEEE CS Press, 1999.
4. D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report 1342, University of Wisconsin Computer Sciences Department, 1997.
5. R. Carl and J. E. Smith. Modeling Superscalar Processors via Statistical Simulation. In Peformance Analysis and It's Impact on Design (PAID) Workshop, pages 1-13, 1998.
6. T. M. Conte, M. A. Hirsch, and K. N. Menezes. Reducing State Loss for Effective Trace Sampling of Superscalar Processors. In IEEE International Conference on Computer Design, pages 468-477, 1996.
7. J.-L. Cruz, A. Gonzalez, and M. Valero. Multiple-Banked Register File Architectures. In The 27th Annual International Symposium on Computer Architecture, pages 316-324, 2000.
8. J. W. C. Fu and J. H. Patel. Trace Driven Simulation using Sampled Traces. In IEEE 27th Hawaii International Conference on System Sciences, 1994.
9. V. S. Iyengar, L. H. Trevillyan, and P. Bose. Representative Traces for Processor Models with Infinite Cache. In The 2nd IEEE Symposium on High Performance Computer Architecture, pages 62-72, 1996.
10. L. K. John, P. Vasudevan, and J. Sabarinathan. Workload Characterization: Motivation, Goals and Methodology. In L. John and A. M. G. Maynard, editors, Workload Characterization: Methodology and Case Studies. IEEE CS Press, 1999.
11. H. Khalid. Validating Trace-Driven Microarchitectural Simulations. IEEE MICRO, 20(6):76-81, December 2000.
12. A. M. G. Maynard, C. M. Donnelly, and B. R. Olszewski. Contrasting Characteristics and Cache Performance of technical and Multi-User Commercial Workloads. In ASPLOS VI, pages 145-155, 1994.
13. S. A. McKee and W. A. Wulf. A Memory Controller for Improved Performance of Streamed Computations on Symmetric Multiprocessors. In The 25th International Conference on Parallel Processing, pages 145-155, 1996.
14. A.-T. Nguyen, P. Bose, K. Ekanadham, A. Nanda, and M. Michael. Accuracy and Speed-Up of Parallel Trace-Driven Architectural Simulation. In The 11th International Parallel Processing Symposium, pages 39-44, 1997.
15. D. B. Noonburg and J. P. Shen. A Framework for Statistical Modeling of Superscalar Processor Performance. In Third International Symposium on High-Performance Computer Architecture, pages 298-309, 1997.
16. M. Oskin, F. T. Chong, and M. Farrens. HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs. In The 27th International Symposium on Computer Architecture, pages 71-82, 2000.
17. A. Poursepanj. The PowerPC Performance Modeling Methodology. Communications of the ACM, 37:47-55, June 1994.