Design of complementary low-power CMOS architectures for looser-take-all and winner-take-all

Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, MicroNeuro 1999

Volumn , Issue , 1999, Pages 360-365

  Donckers, N ^a   Dualibe, C ^a,b   Verleysen, M ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^b UNIVERSIDAD CATÓLICA DE CÓRDOBA   (Argentina)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FUZZY LOGIC; INTEGRATED CIRCUIT DESIGN; MICROELECTRONICS;

LOW POWER CMOS; LOW VOLTAGES; NOVEL ARCHITECTURE; RISETIMES; SPEED CHARACTERISTICS; TAKE-ALL; WINNER TAKE ALLS;

FUZZY INFERENCE;

EID: 84962130113     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MN.1999.758887     Document Type: Conference Paper

References (11)

1. Joongho Choi and Bing J. Sheu "A High-precision VLSI Winner-take-all circuit for self-organizing neural networks" IEEE JSSC vol. 28 n5 may 1993
2. Andreas Demosthenous, Sean Smedley, and John Taylor " A CMOS Analog winner-take-all Networks for Large-Scale Applications" IEEE Transactions on circuits and systems I, vol. 45 n3, pp. 300-303, march 1998
3. Damien Macq, Michel Verleysen, Paul Jespers, and Jean-Didier Legat, "Analog implementation of Kohonen Map with On-Chip Learning" IEEE Transactions on Neural Networks, vol. 4, n3, May 1993
4. Joydeep Ghosh, Ajat Hukkoo, and Anjun Varma, "Neural Networks for Fast Arbitration and Switchnig Noise Reuction in Large Crossbars" IEEE Transactions on circuits and systems, vol. 38, n8, August 1991
5. J. Lazzaro, S. Ryckebush, M. A. Mahowald, and C. A. Mead "Winner-take-all networks of O(n) complexity" in Advances in neural information processing system vol. 1, D. S. Touretsky, Ed. Los Altos, CA : Morgan Kaufman, 1989, pp. 703-711
6. Z. Sezguin Gunay and Edgar Sanchez-Simencio. "CMOS winner-take-all circuits a detail comparaison", Proceedings of ISCAS'97, vol.1, pp. 41-44, Hong-Kong, June 1997
7. P. Thissen "Architectures de circuits massivement paralleles pour la classification par methodes neuronales", pp. 149-152, Ph. D. thesis (in French), Universite Catholique de Louvain, Belgium, 1996
8. M. Verleysen, P. Thissen, J.-L. Voz, J. Madrenas, "An analog processor architecture for a neural network classifier", IEEE Micro vol. 14, n3, June 1994
9. J-P Eggermont, D. Ceuster, D. Flandre, B. Gentinnes, Paul G. A. Jespers, J-P Collinge, "Design of SOI CMOS Operational Amplifier for Applications up to 300C" IEEE JSSC vol. 31 n2 February 1996
10. Christian C. Enz, FranCois Krummenacher and Eric A. Vittoz, "An Analytical MOS Transistor Model Valid in All Regions of Operations and Dedicated to Low-Voltage and Low-Current Applications" Analog Integrated Circuits and Signal Processing 8, pp 86-114 (1995)
11. Elfadel and Wyatt, Advances in Neural Information Processing System 6, p. 882 Cowan, Tesauro and Alspector, Morgan Kaufman