-
1
-
-
0029271036
-
Test Pattern Generation for Path Delay Faults using Binary Decision Diagrams
-
March
-
D. Bhattacharya, P. Agrawal and V.D. Agrawal, "Test Pattern Generation for Path Delay Faults using Binary Decision Diagrams", IEEE Transactions on Computers, vol.44, no.3, pp. 434-447, March 1995.
-
(1995)
IEEE Transactions on Computers
, vol.44
, Issue.3
, pp. 434-447
-
-
Bhattacharya, D.1
Agrawal, P.2
Agrawal, V.D.3
-
2
-
-
0027802093
-
Generation of compact delay tests by multiple path activation
-
S. Bose, P. Agrawal, and V.D. Agrawal, "Generation of compact delay tests by multiple path activation", Proceedings International Test Conference, pp. 714-723, 1993.
-
(1993)
Proceedings International Test Conference
, pp. 714-723
-
-
Bose, S.1
Agrawal, P.2
Agrawal, V.D.3
-
6
-
-
0026677425
-
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
-
K.T. Cheng, et al., "A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits", Proceedings International Test Conference, pp. 403-410, 1991.
-
(1991)
Proceedings International Test Conference
, pp. 403-410
-
-
Cheng, K.T.1
-
7
-
-
0028714176
-
BiTes: A BDD based Test Pattern Generator for Strong Robust Path Delay Faults
-
R. Drechsler, "BiTes: A BDD based Test Pattern Generator for Strong Robust Path Delay Faults", Proceedings European Design and Test Conference, pp. 322-327, 1994.
-
(1994)
Proceedings European Design and Test Conference
, pp. 322-327
-
-
Drechsler, R.1
-
8
-
-
0028727371
-
RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults
-
K. Fuchs, M. Pabst, and T. Roessel, "RESIST: A Recursive Test Pattern Generation Algorithm for Path Delay Faults," Proceedings European Design Automation Conference, pp. 316-321, 1994.
-
(1994)
Proceedings European Design Automation Conference
, pp. 316-321
-
-
Fuchs, K.1
Pabst, M.2
Roessel, T.3
-
9
-
-
0031095781
-
Improved nonenumerative path delay fault coverage estimation based on optimal polynomial time algorithms
-
March
-
D. Kagaris, S. Tragoudas, and D. Karayiannis, "Improved nonenumerative path delay fault coverage estimation based on optimal polynomial time algorithms", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.17, pp. 309-315, March 1997.
-
(1997)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.17
, pp. 309-315
-
-
Kagaris, D.1
Tragoudas, S.2
Karayiannis, D.3
-
11
-
-
0032319936
-
A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
-
Monterey CA, April
-
D. Karayiannis and S. Tragoudas, "A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults", Proceedings 16th IEEE VLSI Test Symposium, pp. 440-445, Monterey CA, April 1998.
-
(1998)
Proceedings 16th IEEE VLSI Test Symposium
, pp. 440-445
-
-
Karayiannis, D.1
Tragoudas, S.2
-
12
-
-
0032691216
-
A Fast Nonenumerative Automatic Test Pattern Generator for Path Delay Faults
-
July
-
D. Karayiannis and S. Tragoudas, "A Fast Nonenumerative Automatic Test Pattern Generator for Path Delay Faults", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.18, no.7, pp. 1050-1057, July 1999.
-
(1999)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.18
, Issue.7
, pp. 1050-1057
-
-
Karayiannis, D.1
Tragoudas, S.2
-
13
-
-
0030402726
-
Identification and test generation of primitive faults
-
A. Krstic, K.-T. Cheng, and S.T. Chakradhar, "Identification and test generation of primitive faults", Proceedings Internation Test Conference, pp. 423-432, 1996.
-
(1996)
Proceedings Internation Test Conference
, pp. 423-432
-
-
Krstic, A.1
Cheng, K.-T.2
Chakradhar, S.T.3
-
14
-
-
0029547554
-
NEST: A Nonenumerative Test Generation Method for Path Delay Faults in Combinational Circuits
-
Dec
-
I. Pomeranz, S. M. Reddy and P. Uppaluri, "NEST: A Nonenumerative Test Generation Method for Path Delay Faults in Combinational Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.14, no.12, pp. 1505-1515, Dec. 1995.
-
(1995)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.14
, Issue.12
, pp. 1505-1515
-
-
Pomeranz, I.1
Reddy, S.M.2
Uppaluri, P.3
-
17
-
-
0027803336
-
A method to derive compact test sets for path delay faults in combinational circuits
-
J. Saxena and D.K. Pradhan, "A method to derive compact test sets for path delay faults in combinational circuits", Proceedings International Test Conference, pp. 724-733, 1993.
-
(1993)
Proceedings International Test Conference
, pp. 724-733
-
-
Saxena, J.1
Pradhan, D.K.2
-
18
-
-
0004000699
-
-
Department of Electrical and Computer Engineering, The University of Colorado at Boulder, release 2.3.0
-
F. Somenzi, "CUDD: CU Decision Diagram Package", Department of Electrical and Computer Engineering, The University of Colorado at Boulder, release 2.3.0, 1999.
-
(1999)
CUDD: CU Decision Diagram Package
-
-
Somenzi, F.1
|