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Volumn , Issue , 2000, Pages 159-164

Functional-based ATPG for path delay faults

Author keywords

[No Author keywords available]

Indexed keywords

MIXED SIGNAL INTEGRATED CIRCUITS;

EID: 84961992326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2000.836465     Document Type: Conference Paper
Times cited : (3)

References (18)
  • 1
    • 0029271036 scopus 로고
    • Test Pattern Generation for Path Delay Faults using Binary Decision Diagrams
    • March
    • D. Bhattacharya, P. Agrawal and V.D. Agrawal, "Test Pattern Generation for Path Delay Faults using Binary Decision Diagrams", IEEE Transactions on Computers, vol.44, no.3, pp. 434-447, March 1995.
    • (1995) IEEE Transactions on Computers , vol.44 , Issue.3 , pp. 434-447
    • Bhattacharya, D.1    Agrawal, P.2    Agrawal, V.D.3
  • 6
    • 0026677425 scopus 로고
    • A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
    • K.T. Cheng, et al., "A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits", Proceedings International Test Conference, pp. 403-410, 1991.
    • (1991) Proceedings International Test Conference , pp. 403-410
    • Cheng, K.T.1
  • 7
    • 0028714176 scopus 로고
    • BiTes: A BDD based Test Pattern Generator for Strong Robust Path Delay Faults
    • R. Drechsler, "BiTes: A BDD based Test Pattern Generator for Strong Robust Path Delay Faults", Proceedings European Design and Test Conference, pp. 322-327, 1994.
    • (1994) Proceedings European Design and Test Conference , pp. 322-327
    • Drechsler, R.1
  • 11
    • 0032319936 scopus 로고    scopus 로고
    • A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
    • Monterey CA, April
    • D. Karayiannis and S. Tragoudas, "A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults", Proceedings 16th IEEE VLSI Test Symposium, pp. 440-445, Monterey CA, April 1998.
    • (1998) Proceedings 16th IEEE VLSI Test Symposium , pp. 440-445
    • Karayiannis, D.1    Tragoudas, S.2
  • 17
    • 0027803336 scopus 로고
    • A method to derive compact test sets for path delay faults in combinational circuits
    • J. Saxena and D.K. Pradhan, "A method to derive compact test sets for path delay faults in combinational circuits", Proceedings International Test Conference, pp. 724-733, 1993.
    • (1993) Proceedings International Test Conference , pp. 724-733
    • Saxena, J.1    Pradhan, D.K.2
  • 18
    • 0004000699 scopus 로고    scopus 로고
    • Department of Electrical and Computer Engineering, The University of Colorado at Boulder, release 2.3.0
    • F. Somenzi, "CUDD: CU Decision Diagram Package", Department of Electrical and Computer Engineering, The University of Colorado at Boulder, release 2.3.0, 1999.
    • (1999) CUDD: CU Decision Diagram Package
    • Somenzi, F.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.