-
1
-
-
84876591853
-
Neural acceleration for general-purpose approximate programs
-
Vancouver, BC, Canada
-
H. Esmaeilzadeh, A. Sampson, L. Ceze, and D. Burger, "Neural acceleration for general-purpose approximate programs, " in Proc. Int. Symp. Microarchit. (MICRO), Vancouver, BC, Canada, 2012, pp. 449-460.
-
(2012)
Proc. Int. Symp. Microarchit. (MICRO)
, pp. 449-460
-
-
Esmaeilzadeh, H.1
Sampson, A.2
Ceze, L.3
Burger, D.4
-
3
-
-
84873704163
-
-
NVIDIA Corp. Santa Clara, CA USA
-
Tesla® Kepler GPU Accelerators, NVIDIA Corp., Santa Clara, CA, USA, 2012. [Online]. Available: http://www.nvidia.com/content/tesla/pdf/tesla-kseries-overview-lr.pdf
-
(2012)
Tesla® Kepler GPU Accelerators
-
-
-
5
-
-
80052528714
-
Dark silicon and the end of multicore scaling
-
San Jose, CA, USA
-
H. Esmaeilzadeh, E. Blem, R. S. Amant, K. Sankaralingam, and D. Burger, "Dark silicon and the end of multicore scaling, " in Proc. IEEE 38th Annu. Int. Symp. Comput. Archit. (ISCA), San Jose, CA, USA, 2011, pp. 365-376.
-
(2011)
Proc IEEE 38th Annu. Int. Symp. Comput. Archit. (ISCA)
, pp. 365-376
-
-
Esmaeilzadeh, H.1
Blem, E.2
Amant, R.S.3
Sankaralingam, K.4
Burger, D.5
-
6
-
-
77956201221
-
Best-effort computing: Re-Thinking parallel software and hardware
-
Anaheim, CA, USA, Jun
-
S. T. Chakradhar and A. Raghunathan, "Best-effort computing: Re-Thinking parallel software and hardware, " in Proc. 47th ACM/IEEE Design Autom. Conf. (DAC), Anaheim, CA, USA, Jun. 2010, pp. 865-870.
-
(2010)
Proc. 47th ACM/ IEEE Design Autom. Conf. (DAC)
, pp. 865-870
-
-
Chakradhar, S.T.1
Raghunathan, A.2
-
7
-
-
84893360544
-
On reconfigurationoriented approximate adder design and its application
-
San Jose, CA, USA
-
R. Ye, T. Wang, F. Yuan, R. Kumar, and Q. Xu, "On reconfigurationoriented approximate adder design and its application, " in Proc. Int. Conf. Comput.-Aided Design, San Jose, CA, USA, 2013, pp. 48-54.
-
(2013)
Proc. Int. Conf. Comput.-Aided Design
, pp. 48-54
-
-
Ye, R.1
Wang, T.2
Yuan, F.3
Kumar, R.4
Xu, Q.5
-
8
-
-
84892524324
-
Quality programmable vector processors for approximate computing
-
Davis, CA, USA
-
S. Venkataramani, V. K. Chippa, S. T. Chakradhar, K. Roy, and A. Raghunathan, "Quality programmable vector processors for approximate computing, " in Proc. 46th Annu. IEEE/ACM Int. Symp. Microarchit., Davis, CA, USA, 2013, pp. 1-12.
-
(2013)
Proc. 46th Annu IEEE/ACM Int. Symp. Microarchit
, pp. 1-12
-
-
Venkataramani, S.1
Chippa, V.K.2
Chakradhar, S.T.3
Roy, K.4
Raghunathan, A.5
-
9
-
-
84871997982
-
Low-power digital signal processing using approximate adders
-
Jan
-
V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, "Low-power digital signal processing using approximate adders, " IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp. 124-137, Jan. 2013.
-
(2013)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.32
, Issue.1
, pp. 124-137
-
-
Gupta, V.1
Mohapatra, D.2
Raghunathan, A.3
Roy, K.4
-
10
-
-
84863541914
-
SALSA: Systematic logic synthesis of approximate circuits
-
San Francisco, CA, USA
-
S. Venkataramani, A. Sabne, V. Kozhikkottu, K. Roy, and A. Raghunathan, "SALSA: Systematic logic synthesis of approximate circuits, " in Proc. 49th Annu. Design Autom. Conf., San Francisco, CA, USA, 2012, pp. 796-801.
-
(2012)
Proc. 49th Annu. Design Autom. Conf
, pp. 796-801
-
-
Venkataramani, S.1
Sabne, A.2
Kozhikkottu, V.3
Roy, K.4
Raghunathan, A.5
-
11
-
-
84903850362
-
A low-power, high-performance approximate multiplier with configurable partial error recovery
-
Dresden, Germany, Art. ID 95
-
C. Liu, J. Han, and F. Lomardi, "A low-power, high-performance approximate multiplier with configurable partial error recovery, " in Proc. Conf. Design Autom. Test Europe, Dresden, Germany, 2014, Art. ID 95.
-
(2014)
Proc. Conf. Design Autom. Test Europe
-
-
Liu, C.1
Han, J.2
Lomardi, F.3
-
12
-
-
84903842142
-
Video analytics using beyond CMOS devices
-
V. Narayanan et al., "Video analytics using beyond CMOS devices, " in Proc. Conf. Design, Autom. Test Europe (DATE), Dresden, Germany, 2014, pp. 1-5.
-
(2014)
Proc. Conf. Design, Autom. Test Europe (DATE), Dresden, Germany
, pp. 1-5
-
-
Narayanan, V.1
-
13
-
-
84889601634
-
Memristor-based approximated computation
-
Sep
-
B. Li et al., "Memristor-based approximated computation, " in Proc. IEEE Int. Symp. Low Power Electron. Design (ISLPED), Beijing, China, Sep. 2013, pp. 242-247.
-
(2013)
Proc IEEE Int. Symp. Low Power Electron. Design (ISLPED), Beijing, China
, pp. 242-247
-
-
Li, B.1
-
14
-
-
79957568212
-
Design implications of memristor-based RRAM cross-point structures
-
C. Xu, X. Dong, N. P. Jouppi, and Y. Xie, "Design implications of memristor-based RRAM cross-point structures, " in Proc. IEEE Design, Autom. Test Eur. Conf. Exhibit. (DATE), Grenoble, France, 2011, pp. 1-6.
-
(2011)
Proc IEEE Design, Autom. Test Eur. Conf. Exhibit. (DATE), Grenoble, France
, pp. 1-6
-
-
Xu, C.1
Dong, X.2
Jouppi, N.P.3
Xie, Y.4
-
15
-
-
77951026760
-
Nanoscale memristor device as synapse in neuromorphic systems
-
S. H. Jo et al., "Nanoscale memristor device as synapse in neuromorphic systems, " Nano Lett., vol. 10, no. 4, pp. 1297-1301, 2010.
-
(2010)
Nano Lett
, vol.10
, Issue.4
, pp. 1297-1301
-
-
Jo, S.H.1
-
16
-
-
84863553133
-
Hardware realization of BSB recall function using memristor crossbar arrays
-
San Francisco, CA, USA
-
M. Hu, H. Li, Q. Wu, and G. S. Rose, "Hardware realization of BSB recall function using memristor crossbar arrays, " in Proc. Design Autom. Conf., San Francisco, CA, USA, 2012, pp. 498-503.
-
(2012)
Proc. Design Autom. Conf
, pp. 498-503
-
-
Hu, M.1
Li, H.2
Wu, Q.3
Rose, G.S.4
-
17
-
-
84861125089
-
Metal-oxide RRAM
-
Jun
-
H.-S. P. Wong et al., "Metal-oxide RRAM, " Proc. IEEE, vol. 100, no. 6, pp. 1951-1970, Jun. 2012.
-
(2012)
Proc IEEE
, vol.100
, Issue.6
, pp. 1951-1970
-
-
Wong, H.-S.P.1
-
18
-
-
84875158827
-
A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation
-
Mar
-
S. Yu et al., "A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation, " Adv. Mater., vol. 25, no. 12, pp. 1774-1779, Mar. 2013.
-
(2013)
Adv. Mater
, vol.25
, Issue.12
, pp. 1774-1779
-
-
Yu, S.1
-
19
-
-
84872848395
-
RRAM crossbar array with cell selection device: A device and circuit interaction study
-
Feb
-
Y. Deng et al., "RRAM crossbar array with cell selection device: A device and circuit interaction study, " IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 719-726, Feb. 2013.
-
(2013)
IEEE Trans. Electron Devices
, vol.60
, Issue.2
, pp. 719-726
-
-
Deng, Y.1
-
20
-
-
84856173450
-
High precision tuning of state for memristive devices by adaptable variation-Tolerant algorithm
-
Art. ID 075201
-
F. Alibart, L. Gao, B. D. Hoskins, and D. B. Strukov, "High precision tuning of state for memristive devices by adaptable variation-Tolerant algorithm, " Nanotechnology, vol. 23, no. 7, 2012, Art. ID 075201.
-
(2012)
Nanotechnology
, vol.23
, Issue.7
-
-
Alibart, F.1
Gao, L.2
Hoskins, B.D.3
Strukov, D.B.4
-
21
-
-
84866886745
-
A SPICE compact model of metal oxide resistive switching memory with variations
-
Oct
-
X. Guan, S. Yu, and H.-S. P. Wong, "A SPICE compact model of metal oxide resistive switching memory with variations, " IEEE Electron Device Lett., vol. 33, no. 10, pp. 1405-1407, Oct. 2012.
-
(2012)
IEEE Electron Device Lett
, vol.33
, Issue.10
, pp. 1405-1407
-
-
Guan, X.1
Yu, S.2
Wong, H.-S.P.3
-
22
-
-
0024880831
-
Multilayer feedforward networks are universal approximators
-
K. Hornik, M. Stinchcombe, and H. White, "Multilayer feedforward networks are universal approximators, " Neural Netw., vol. 2, no. 5, pp. 359-366, 1989.
-
(1989)
Neural Netw
, vol.2
, Issue.5
, pp. 359-366
-
-
Hornik, K.1
Stinchcombe, M.2
White, H.3
-
23
-
-
0013448852
-
Approximation capability of layered neural networks with sigmoid units on two layers
-
Nov
-
Y. Ito, "Approximation capability of layered neural networks with sigmoid units on two layers, " Neural Comput., vol. 6, no. 6, pp. 1233-1243, Nov. 1994.
-
(1994)
Neural Comput
, vol.6
, Issue.6
, pp. 1233-1243
-
-
Ito, Y.1
-
24
-
-
0003710566
-
-
Upper Saddle River, NJ, USA, Prentice-Hall
-
L. Fausett, Ed., Fundamentals of Neural Networks: Architectures, Algorithms, and Applications. Upper Saddle River, NJ, USA: Prentice-Hall, 1994.
-
(1994)
Fundamentals of Neural Networks: Architectures, Algorithms, and Applications
-
-
Fausett, L.1
-
25
-
-
84926459123
-
Technological exploration of RRAM crossbar array for matrix-vector multiplication
-
Chiba, Japan
-
P. Gu et al., "Technological exploration of RRAM crossbar array for matrix-vector multiplication, " in Proc. IEEE 20th Asia South Pac. Design Autom. Conf. (ASPDAC), Chiba, Japan, 2015, pp. 106-111.
-
(2015)
Proc IEEE 20th Asia South Pac. Design Autom. Conf. (ASPDAC)
, pp. 106-111
-
-
Gu, P.1
-
26
-
-
34248632007
-
Design procedures for three-stage CMOS OTAs with nested-miller compensation
-
May
-
S. O. Cannizzaro, A. D. Grasso, R. Mita, G. Palumbo, and S. Pennisi, "Design procedures for three-stage CMOS OTAs with nested-miller compensation, " IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 5, pp. 933-940, May 2007.
-
(2007)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.54
, Issue.5
, pp. 933-940
-
-
Cannizzaro, S.O.1
Grasso, A.D.2
Mita, R.3
Palumbo, G.4
Pennisi, S.5
-
27
-
-
36248933177
-
A CMOS low-dropout regulator with current-mode feedback buffer amplifier
-
Oct
-
W. Oh and B. Bakkaloglu, "A CMOS low-dropout regulator with current-mode feedback buffer amplifier, " IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 10, pp. 922-926, Oct. 2007.
-
(2007)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.54
, Issue.10
, pp. 922-926
-
-
Oh, W.1
Bakkaloglu, B.2
-
29
-
-
84903846638
-
ICE: Inline calibration for memristor crossbar-based computing engine
-
Dresden, Germany
-
B. Li, Y. Wang, Y. Chen, H. H. Li, and H. Yang, "ICE: Inline calibration for memristor crossbar-based computing engine, " in Proc. Conf. Design Autom. Test Europe, Dresden, Germany, 2014, pp. 1-4.
-
(2014)
Proc. Conf. Design Autom. Test Europe
, pp. 1-4
-
-
Li, B.1
Wang, Y.2
Chen, Y.3
Li, H.H.4
Yang, H.5
-
30
-
-
84859005353
-
Analog implementation of a novel resistive-Type sigmoidal neuron
-
Apr
-
G. Khodabandehloo, M. Mirhassani, and M. Ahmadi, "Analog implementation of a novel resistive-Type sigmoidal neuron, " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 4, pp. 750-754, Apr. 2012.
-
(2012)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.20
, Issue.4
, pp. 750-754
-
-
Khodabandehloo, G.1
Mirhassani, M.2
Ahmadi, M.3
-
31
-
-
0001219859
-
Regularization theory and neural networks architectures
-
F. Girosi, M. Jones, and T. Poggio, "Regularization theory and neural networks architectures, " Neural Comput., vol. 7, no. 2, pp. 219-269, 1995.
-
(1995)
Neural Comput
, vol.7
, Issue.2
, pp. 219-269
-
-
Girosi, F.1
Jones, M.2
Poggio, T.3
-
32
-
-
58149231291
-
A bipolar-selected phase change memory featuring multi-level cell storage
-
Jan
-
F. Bedeschi et al., "A bipolar-selected phase change memory featuring multi-level cell storage, " IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 217-227, Jan. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.1
, pp. 217-227
-
-
Bedeschi, F.1
-
33
-
-
64549149261
-
Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM
-
San Francisco, CA, USA
-
H. Y. Lee et al., "Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM, " in Proc. IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2008, pp. 1-4.
-
(2008)
Proc IEEE Int. Electron Devices Meeting (IEDM)
, pp. 1-4
-
-
Lee, H.Y.1
-
34
-
-
84877844855
-
Sneak-path testing of crossbar-based nonvolatile random access memories
-
May
-
S. Kannan, J. Rajendran, R. Karri, and O. Sinanoglu, "Sneak-path testing of crossbar-based nonvolatile random access memories, " IEEE Trans. Nanotechnol., vol. 12, no. 3, pp. 413-426, May 2013.
-
(2013)
IEEE Trans. Nanotechnol
, vol.12
, Issue.3
, pp. 413-426
-
-
Kannan, S.1
Rajendran, J.2
Karri, R.3
Sinanoglu, O.4
-
35
-
-
84871827258
-
-
International Roadmap Committee Semicond. Ind. Assoc., San Francisco, CA, USA
-
International Roadmap Committee, International Technology Roadmap for Semiconductors: 2013 Edition, Semicond. Ind. Assoc., San Francisco, CA, USA, 2013. [Online]. Available: http://www.itrs.net/ITRS%201999-2014%20Mtgs, %20Presentations% 20&%20Links/2013ITRS/Summary2013.htm
-
(2013)
International Technology Roadmap for Semiconductors 2013 Edition
-
-
-
36
-
-
0032316337
-
A high-swing CMOS telescopic operational amplifier
-
Dec
-
K. Gulati and H.-S. Lee, "A high-swing CMOS telescopic operational amplifier, " IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2010-2019, Dec. 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, Issue.12
, pp. 2010-2019
-
-
Gulati, K.1
Lee, H.-S.2
-
37
-
-
84876531800
-
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
-
San Francisco, CA, USA
-
L. Kull et al., "A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS, " in ISSCC Dig. Tech. Papers, San Francisco, CA, USA, 2013, pp. 468-469.
-
(2013)
ISSCC Dig. Tech. Papers
, pp. 468-469
-
-
Kull, L.1
-
38
-
-
84876564986
-
A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth
-
W.-T. Lin and T.-H. Kuo, "A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth, " in ISSCC Dig. Tech. Papers, San Francisco, CA, USA, 2013, pp. 474-475.
-
(2013)
ISSCC Dig. Tech. Papers, San Francisco, CA, USA
, pp. 474-475
-
-
Lin, W.-T.1
Kuo, T.-H.2
-
39
-
-
51149092609
-
Object class recognition and localization using sparse features with limited receptive fields
-
Oct
-
J. Mutch and D. G. Lowe, "Object class recognition and localization using sparse features with limited receptive fields, " Int. J. Comput. Vis., vol. 80, no. 1, pp. 45-57, Oct. 2008.
-
(2008)
Int. J. Comput. Vis
, vol.80
, Issue.1
, pp. 45-57
-
-
Mutch, J.1
Lowe, D.G.2
-
40
-
-
84863551827
-
Accelerating neuromorphic vision algorithms for recognition
-
San Francisco, CA, USA
-
A. A. Maashri et al., "Accelerating neuromorphic vision algorithms for recognition, " in Proc. 49th Annu. Design Autom. Conf., San Francisco, CA, USA, 2012, pp. 579-584.
-
(2012)
Proc. 49th Annu. Design Autom. Conf
, pp. 579-584
-
-
Maashri, A.A.1
-
41
-
-
77951298115
-
The PASCAL visual object classes (VOC) challenge
-
M. Everingham, L. Van Gool, C. K. Williams, J. Winn, and A. Zisserman, "The PASCAL visual object classes (VOC) challenge, " Int. J. Comp. Vis., vol. 88, no. 2, pp. 303-338, 2010.
-
(2010)
Int. J. Comp. Vis
, vol.88
, Issue.2
, pp. 303-338
-
-
Everingham, M.1
Van Gool, L.2
Williams, C.K.3
Winn, J.4
Zisserman, A.5
-
42
-
-
80052097231
-
Impact of temperature on the resistive switching behavior of embedded HfO2-based RRAM devices
-
Sep
-
C. Walczyk et al., "Impact of temperature on the resistive switching behavior of embedded HfO2-based RRAM devices, " IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3124-3131, Sep. 2011.
-
(2011)
IEEE Trans. Electron Devices
, vol.58
, Issue.9
, pp. 3124-3131
-
-
Walczyk, C.1
|