CVD barriers for Cu with nanoporous ultra low-k: Integration and reliability

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 21-23

  Lin, J C ^a,b   Augur, R ^a,c   Shue, S L ^b   Yu, C H ^b   Liang, M S ^b   Vijayendran, A ^d   Suwwan De Felipe, T ^d   Danek, M ^d  

^a SEMATECH   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c NXP SEMICONDUCTORS   (Netherlands)

^d Novellus Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; INTEGRATED CIRCUITS; LOW-K DIELECTRIC;

CIRCUIT PERFORMANCE; DUAL DAMASCENE INTEGRATION; FEASIBILITY STUDIES; INTERCONNECT SYSTEMS; NANO-POROUS; POROUS STRUCTURES; POROUS ULTRA LOW-K; ULTRA LOW-K;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84961711496     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014875     Document Type: Conference Paper

References (5)

1. The International Technology Roadmap for Semiconductors, 2001 Edition, Semiconductor Industry Association, San Jose, CA (2001)
2. K. Mosig, H. Cox, E. Klawuhn, T. Suwwan de Felipe, A. Shiota, IEDM, Section 4. 2001.
3. H.S. Choe, M. Danek, Proceedings of the IITC 1999, 62, IEEE, Piscataway, NJ (1999)
4. T. Jacobs et al, unpublished results.
5. T. Suwwan de Felipe et al, Proceedings of AMC, Montreal 2001, in press.