Via first dual damascene integration of nanoporous ultra low-k material

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 48-50

  Lin, J C ^a,b   Lee, H S ^a,c   Satyanarayana, S ^a   Martinez, H ^a,d   Jacobs, T ^a,e   Brennan, K ^a,f   Gonzalez, A ^a   Augur, R ^a,d   Shue, S L ^b   Yu, C H ^b   Liang, M S ^b  

^a SEMATECH   (United States)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^c Hynix Semiconductor Inc   (South Korea)

^d MOTOROLA INC   (United States)

^e Philip Semiconductors   (Netherlands)

^f TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATION; LOW-K DIELECTRIC;

CAP LAYERS; DUAL DAMASCENE INTEGRATION; DUAL DAMASCENE STRUCTURES; NANO-POROUS; POROUS DIELECTRICS; POROUS ULTRA LOW-K; ULTRA LOW K MATERIALS; VIA FIRST;

DIELECTRIC MATERIALS;

EID: 84961692346     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014883     Document Type: Conference Paper

References (4)

1. S. W. Russel et al, Proc. ULSI XIII, 1998, p289-300.
2. S. Lin et al. Intl. Interconnect Tech. Conf. (IITC), 2001, p146-148.
3. K. Mosig et al, Intl. Interconnect Tech. Conf. (IITC), 2001, p292-294.
4. J. C. Lin, unpublished results.