Nonvolatile logic-in-memory LSI using cycle-based power gating and its application to motion-vector prediction

IEEE Journal of Solid-State Circuits

Volumn 50, Issue 2, 2015, Pages 476-489

  Natsui, Masanori ^a   Suzuki, Daisuke ^a   Sakimura, Noboru ^b   Nebashi, Ryusuke ^b   Tsuji, Yukihide ^b   Morioka, Ayuka ^b   Sugibayashi, Tadahiko ^b   Miura, Sadahiko ^b   Honjo, Hiroaki ^a,b   Kinoshita, Keizo ^a,c   Ikeda, Shoji ^a   Endoh, Tetsuo ^a   Ohno, Hideo ^a   Hanyu, Takahiro ^a  

^a TOHOKU UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

^c SCR   (Japan)

Author keywords

Automated design environment; magnetic tunnel junction (MTJ); motion vector prediction; nonvolatile logic in memory (NV LIM); power gating; spin transfer torque random access memory (STT RAM)

Indexed keywords

AUTOMATION; COMPUTER CIRCUITS; FABRICATION; FORECASTING; LOGIC DESIGN; LSI CIRCUITS; MAGNETIC DEVICES; MOTION ESTIMATION; TUNNEL JUNCTIONS;

AUTOMATED DESIGN; MAGNETIC TUNNEL JUNCTION; MOTION VECTOR PREDICTION; NON-VOLATILE LOGIC; POWER GATINGS; SPIN-TRANSFER TORQUE RANDOM ACCESS MEMORY (STT-RAM);

RANDOM ACCESS STORAGE;

EID: 84961315489     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2014.2362853     Document Type: Article

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