Another trip to the wall: how much will stacked dram benefit HPC?

ACM International Conference Proceeding Series

Volumn 05-08-October-2015, Issue , 2015, Pages 31-36

  Radulovic, Milan ^a   Zivanovic, Darko ^a   Ruiz, Daniel ^a   De Supinski, Bronis R ^b   McKee, Sally A ^c   Radojkovíc, Petar ^a   Ayguad, Eduard ^a  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

^c CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

Bandwidth; Dram; High bandwidth memory (hbm); Hpc; Hybrid memory cube (hmc); Latency; Memory wall

Indexed keywords

BANDWIDTH; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3D STACKING TECHNOLOGY; 3D-STACKED DRAMS; FUNDAMENTAL LIMITATIONS; HIGH BANDWIDTH; HYBRID MEMORY; LATENCY; MEMORY WALL; TECHNOLOGICAL INNOVATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84959346172     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2818950.2818955     Document Type: Conference Paper

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