Design considerations of HBM stacked DRAM and the memory architecture extension

Proceedings of the Custom Integrated Circuits Conference

Volumn 2015-November, Issue , 2015, Pages

  Lee, Dong Uk ^a   Lee, Kang Seol ^a   Lee, Yongwoo ^a   Kim, Kyung Whan ^a   Kang, Jong Ho ^a   Lee, Jaejin ^a   Chun, Jun Hyun ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

High Bandwidth; Microbump; Multi Channel; Stacked Memory; TSV

Indexed keywords

BANDWIDTH; DYNAMIC RANDOM ACCESS STORAGE; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; RECONFIGURABLE HARDWARE; THREE DIMENSIONAL INTEGRATED CIRCUITS;

DESIGN CONSIDERATIONS; HIGH BANDWIDTH; LOW-POWER CONSUMPTION; MICRO-BUMPS; MULTI CHANNEL; PERFORMANCE ENHANCEMENTS; SMALL FORM FACTORS; STACKED MEMORY;

MEMORY ARCHITECTURE;

EID: 84959219393     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2015.7338357     Document Type: Conference Paper

References (29)

1. E. Doller, et al., "DataCenter 2020: Near-memory Acceleration for Data-oriented Applications," Symposium on VLSI Circuits Digest of Technical Papers, June 2014.
2. J. Y.-C. Sun, "System Scaling and Collaborative Open Innovation," Symposium on VLSI Technology Digest of Technical Papers, pp.2-7, June 2013.
3. K. T. Malladi, et al., "Towards Energy-Proportional Datacenter Memory with Mobile DRAM", Proc. of International Symposium of Computer Architecture (ISCA), pp. 37-48, June 2012
4. J. Kim, C. S. Oh, et al., "A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4x128 I/Os Using TSV-Based Stacking," IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 107-116, Jan. 2012.
5. L. Madden, E. Wu, et al., "Advancing High Performance Heterogeneous Integration Through Die Stacking," European Solid-State Device Research Conference (ESSDERC), pp. 18-24, Sept. 2012.
6. D. Maheshwari, "Memory and System Architecture for 400Gb/s Networking and Beyond," ISSCC Dig. Tech. Papers, pp. 116-117, Feb. 2014.
7. M.-S. Lin. C.-C. Tsai, et al., "An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application," Symposium on VLSI Circuits Digest of Technical Papers, pp.C16-C17, June 2013.
8. D. U. Lee, K. W. Kim, et al., "A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits," IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 191-203, Jan. 2015
9. JEDEC Standard High Bandwidth Memory (HBM) DRAM Specification, 2013.
10. T.-Y. Oh, Y.-S. Sohn, et al., "A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 107-118, Jan. 2011.
11. JEDEC Standard LPDDR3 SDRAM Specification, 2012
12. T. M. Hollis, et al., "Data Bus Inversion in High-Speed Memory Applications," IEEE Transactions on Circuits and Systems II, vol.56, no. 4, pp. 300-304, Apr. 2009.
13. Y.-C. Lai, S.-Y. Huang, "Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)," IEEE J. Solid-State Circuits, vol.44, no.2, pp. 642-648, Feb. 2009
14. S. Ohbayashi, M. Yabuuchi, et.al., "A 65 nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and Cu e-trim fuse for known good die," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 96-108, Jan. 2008.
15. S. Takaya, M. Nagata, et al., "A 100GB/s Wide I/O with 4096b TSVs Through an Active Silicon Interposer with In-Place Waveform Capturing," ISSCC Dig. Tech. Papers, pp. 434-435, Feb. 2013.
16. Y. Liu, W. Luk, et al., "A Compact Low-Power 3D I/O in 45nm CMOS," ISSCC Dig. Tech. Papers, pp. 142-143, Feb. 2012.
17. B. Keller, T. Bartenstein, "Use of MISRs for Compression and Diagnostics," Proc. International Test Conference (ITC), pp. 735-743, Nov. 2005.
18. A.L.S. Loke, B.A. Doyle, et.al, "Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links," Custom Integrated Circuits Conference(CICC), pp.605 - 608, Sept. 2009.
19. J. S. Park, et al., "PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models" IEEE Transactions on Components, Packaging, and Manufacturing Technology, Vol. 1, No. 2, pp.208 - 219, Feb. 2011
20. C. Y. Lee, et al., "TSV Technology and Challenges for 3D Stacked DRAM," Symposium on VLSI Technology Digest of Technical Papers, June 2014.
21. D. U. Lee, et al., "An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM, " Symposium on VLSI Circuits Digest of Technical Papers, June 2014
22. S. Bae et al., "A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques," ISSCC Dig. Tech. Papers, pp. 278-279, Feb. 2008.
23. Shiratake, S, et al., "A pseudo multi-bank DRAM with categorized access sequence," Symposium on VLSI Circuits Digest of Technical Papers, pp.127-130, June 1999.
24. G. Atwood, et al., "A semiconductor memory development and manufacturing perspective," European Solid-State Device Research Conference (ESSDERC), Sept. 2014
25. R. Kho et al., "75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 120-133, Jan. 2010.
26. Yoongu Kim, et al., "A case for exploiting subarray-level parallelism (SALP) in DRAM," International Symposium on Computer Architecture (ISCA), pp. 368-379, 2012
27. Donghyuk Lee, et al., "Tiered-latency DRAM: A low latency and low cost DRAM architecture," International Symposium on High Performance Computer Architecture, pp. 615-626, 2013
28. R. Oh, et al., "Design Technologies for a 1.2V 2.4Gb/s/pin High Capacity DDR4 SDRAM with TSVs," Symposium on VLSI Technology Digest of Technical Papers, June 2014.
29. S.-B. Lim, et al., "A 247 μW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface,"IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 711-722, Mar. 2013