A 16-channel, 1-second latency patient-specific seizure onset and termination detection processor with dual detector architecture and digital hysteresis

Proceedings of the Custom Integrated Circuits Conference

Volumn 2015-November, Issue , 2015, Pages

  Zhang, Chen ^a   Altaf, Muhammad Awais Bin ^a   Yoo, Jerald ^a  

^a KHALIFA UNIVERSITY   (United Arab Emirates)

Author keywords

digital hysteresis; dual detector architecture; epileptic seizure; machine learning; scalp electroencephalography (EEG); seizure onset and termination detection

Indexed keywords

ARTIFICIAL INTELLIGENCE; CLASSIFICATION (OF INFORMATION); ELECTROENCEPHALOGRAPHY; ELECTROPHYSIOLOGY; ENERGY EFFICIENCY; HYSTERESIS; INTEGRATED CIRCUITS; RECONFIGURABLE HARDWARE; TIME DIVISION MULTIPLEXING;

DUAL-DETECTORS; EPILEPTIC SEIZURES; FILTER ARCHITECTURE; LINEAR SUPPORT VECTOR MACHINES; MACHINE LEARNING TECHNIQUES; OVERALL ENERGY EFFICIENCY; PATIENT SPECIFIC; TERMINATION DETECTION;

LEARNING SYSTEMS;

EID: 84959209949     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2015.7338458     Document Type: Conference Paper

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