A quantitative cross-architecture study of morphological image processing on CPUs, GPUs, and FPGAs

ISCAIE 2015 - 2015 IEEE Symposium on Computer Applications and Industrial Electronics

Volumn , Issue , 2015, Pages 201-206

  Brugger, Christian ^a   Dal'Aqua, Lorenzo ^a   Varela, Javier Alejandro ^a   De Schryver, Christian ^a   Sadri, Mohammadsadegh ^a   Wehn, Norbert ^a   Klein, Martin ^b   Siegrist, Michael ^b  

^a University of Koblenz Landau   (Germany)

^b Wipotec Wiege und Positioniersysteme GmbH   (Germany)

Author keywords

Computer architecture; Field programmable gate arrays; Graphics processing units; Hardware; Image processing; Kernel; Libraries

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; COMPUTER HARDWARE; COMPUTER VISION; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; HIGH LEVEL SYNTHESIS; INDUSTRIAL ELECTRONICS; LIBRARIES; MATHEMATICAL MORPHOLOGY; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE;

EFFICIENCY AND PERFORMANCE; EFFICIENT IMPLEMENTATION; FPGA IMPLEMENTATIONS; GRAPHICS PROCESSING UNIT; IMAGE PROCESSING AND COMPUTER VISION; KERNEL; MORPHOLOGICAL IMAGE PROCESSING; MORPHOLOGICAL OPERATIONS;

IMAGE PROCESSING;

EID: 84959038718     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAIE.2015.7298356     Document Type: Conference Paper

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