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Volumn 2027, Issue , 2001, Pages 165-181

Software pipelining of nested loops

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; ITERATIVE METHODS; PIPELINES; PROLOG (PROGRAMMING LANGUAGE);

EID: 84958962354     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45306-7_12     Document Type: Conference Paper
Times cited : (20)

References (17)
  • 1
    • 84956707221 scopus 로고
    • Optimal Loop Parallelization. Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementa- tion
    • Aiken, A., Nicolau, A.: Optimal Loop Parallelization. Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementa- tion, June, (1988), 308-317
    • (1988) June , pp. 308-317
    • Aiken, A.1    Nicolau, A.2
  • 4
    • 0019610938 scopus 로고
    • An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family
    • Charlesworth, A.: An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family. IEEE Computer, Sept. (1981).
    • (1981) IEEE Computer, Sept
    • Charlesworth, A.1
  • 7
    • 84959000451 scopus 로고    scopus 로고
    • A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops
    • January
    • Eisenbeis, C., et al: A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops. INRIA TR-RR3337, January (1998)
    • (1998) INRIA TR-RR3337
    • Eisenbeis, C.1
  • 9
    • 84969390838 scopus 로고    scopus 로고
    • IA-64 Architecture Software Developer's Manual. Santa Clara
    • Intel Corporation: IA-64 Architecture Software Developer's Manual. Santa Clara, CA, April 2000
    • (2000) CA
  • 12
    • 0029202471 scopus 로고
    • A Com- parison of Full and Partial Predicated Execution Support for ILP Processors. Pro- ceedings of the 22nd International Symposium on Computer Architecture
    • Mahlke, S. A., Hank, R. E., McCormick, J.E., August, D. I., Hwu, W. W.: A Com- parison of Full and Partial Predicated Execution Support for ILP Processors. Pro- ceedings of the 22nd International Symposium on Computer Architecture, June, (1995), 138-150
    • (1995) June , pp. 138-150
    • Mahlke, S.A.1    Hank, R.E.2    McCormick, J.E.3    August, D.I.4    Hwu, W.W.5
  • 14
    • 0028768013 scopus 로고
    • Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops
    • Rau, B. R.: Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops. MICRO-27, (1994), 63-74
    • (1994) MICRO-27 , pp. 63-74
    • Rau, B.R.1
  • 15
    • 0026976353 scopus 로고
    • Code Generation Schema for Modulo Scheduled Loops
    • Rau, B. R, Schlansker, M. S., Tirumalai, P. P.: Code Generation Schema for Modulo Scheduled Loops. MICRO-25, (1992), 158-169
    • (1992) MICRO-25 , pp. 158-169
    • Rau, B.R.1    Schlansker, M.S.2    Tirumalai, P.P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.