Fully automatic verification and error detection for parameterized iterative sequential circuits

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1055, Issue , 1996, Pages 258-277

  Margaria, Tiziana ^a  

^a UNIVERSITY OF PASSAU   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR DETECTION; FORMAL LOGIC; RECONFIGURABLE HARDWARE; SEQUENTIAL CIRCUITS;

AUTOMATIC VERIFICATION; COUNTER-MODELS; DECISION PROCEDURE; DETECTION AND DIAGNOSIS; HARDWARE SPECIFICATIONS; ITERATIVE DESIGN; MONADIC SECOND-ORDER LOGIC; VERIFICATION TOOLS;

ITERATIVE METHODS;

EID: 84958745469     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-61042-1_49     Document Type: Conference Paper

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