A 800Mpixel/sec reconfigurable image correlator on XC6216

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1304, Issue , 1997, Pages 382-391

  Kean, Tom ^a   Duncan, Ann ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84957893074     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_243     Document Type: Conference Paper

References (8)

1. Xilinx Inc, “XC6200 FPGA Family Advanced Product Description”, available from Xilinx Inc. 2100 Logic Drive, San Jose, CA
2. Wayne Luk and Nabeel Shirazi, “Modelling and Optimising Run Time Reconfigurable Systems”, Proc IEEE Symposium on FPGAs for Custom Computing Machines, Napa, CA 1996.
3. Tom Kean, “Configurable Logic: A Dynamically Programmable Cellular Architecture and its VLSI Implementation”, PhD Thesis CST62-89, University of Edinburgh, Dept of Computer Science.
4. Tom Kean and John Gray “Configurable Hardware: A new paradigm for computation”, Advanced Research in VLSI, Proc. Decennial Caltech Conference, MIT Press 1989.
5. Brian Von Herzen, “250MHz correlation using high-performance reconfigurable computing engines”, Proc SPIE - The International Society for Optical Engineering, vol. 2914, pp. 34-43.
6. Parallel Counters, Earl E. Swartzlander Jnr. IEEE Trans on Computing C-22, pp 1021-1024 (1973)
7. Tom Kean and John Gray, “Configurable Hardware: Two case studies of micrograin computation”, Systolic Array Processors, Prentice Hall, 1989. Edited by McCanny, McWhirter and Swartzlander, pp 310-319.
8. P.W. Foulk and L.D. Hodgson, “Data folding in SRAM configurable FPGAs”, Proc IEEE Symposium on FPGAs for Custom Computing Machines, Napa, CA 1993