FPGA-accelerated complex event processing

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2015-August, Issue , 2015, Pages C126-C127

  Takenaka, Takashi ^a   Inoue, Hiroaki ^a   Hosomi, Takeo ^a   Nakamura, Yuichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84957890151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2015.7231349     Document Type: Conference Paper

References (6)

1. Putnam, A., et al., ISCA, 2014.
2. Leber, C., et al., FPL, pp. 317-322, 2011.
3. Arasu, M., et al., Int'l Conf. on VLDB, Aug 2004.
4. Inoue, H., et al., FPL, pp. 97-102, 2011.
5. Takenaka, T., et al., FPL, pp. 237-242, 2012.
6. Wakabayashi, K., et al., "High-Level Synthesis", pp. 113-127, 2008.