Fast parallel implementation of DFT using configurable devices

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1304, Issue , 1997, Pages 314-323

  Dandalis, Andreas ^a   Prasanna, Viktor K ^a  

^a University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84957887389     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-63465-7_236     Document Type: Conference Paper

References (12)

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3. S. Choi, Y. Chung and V. K. Prasanna, “Configurable Hardware for Symbolic Search Operations”, submitted to Int. Conf. Parallel and Distributed Systems, Dec. 1997.
4. Y. Chung S. Choi and V. K. Prasanna, “Parallel Object Recognition on an FPGA- based Configurable Computing Platform”, submitted to Int. Workshop on Computer Architecture for Machine Perception, Oct. 1997.
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10. I. S. Reed, M. T. Shih, T. K. Truong, E. Hendon and D. W. Tufts, “A VLSI architecture for simplified arithmetic Fourier transform algorithm”, in Proc. Int. Conf. Application Specific Array Processor, 1990.
11. R. Wilson, “Reprogrammable FPGA-based techniques provide prototyping aid”, Electronic Engineering Times, Mar. 11, 1996.
12. XILINX DSP Application notes, “The Fastest FFT in the West”, http://www.xilinx.com/apps/displit.htm