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Volumn 1606, Issue , 1999, Pages 450-457

Cascade error projection: A learning algorithm for hardware implementation

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HARDWARE; LEARNING SYSTEMS; RECONFIGURABLE HARDWARE; SIGNAL ENCODING;

EID: 84957691661     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0098202     Document Type: Conference Paper
Times cited : (3)

References (12)
  • 2
    • 0028756091 scopus 로고
    • Low Power Analog Neurosynapse Chips for a 3-D "Sugarcube" Neuroprocessor
    • June 28-July 2, Orlando, Florida
    • T.A. Duong et al, "Low Power Analog Neurosynapse Chips for a 3-D "Sugarcube" Neuroprocessor," Proc. of IEEE Intl' Copf on Neural Networks(ICNN/WCCI) Vol 3, pp. 1907-1911, June 28-July 2, 1994, Orlando, Florida.
    • (1994) Proc. Of IEEE Intl' Copf on Neural Networks(Icnn/Wcci) , vol.3 , pp. 1907-1911
    • Duong, T.A.1
  • 4
    • 0000726115 scopus 로고
    • The effects of Precision Constraints in a Backpropagation learning Network
    • P.W. Hollis, J.S. Harper, and ].J. Paulus, "The effects of Precision Constraints in a Backpropagation learning Network," Neural Computation, vol. 2, pp. 363-373, 1990.
    • (1990) Neural Computation , vol.2 , pp. 363-373
    • Hollis, P.W.1    Harper, J.S.2    Paulus, J.3
  • 5
    • 0026896593 scopus 로고
    • Learning with limited numerical precision using the cascade-correlation algorithm
    • M lloehfeld and S. Fahhnan, "Learning with limited numerical precision using the cascade-correlation algorithm," IEEE Trans. Neural Networks, vol.3, No. 4, pp 602-611, July 1992.
    • (1992) IEEE Trans. Neural Networks , vol.3 , Issue.4 , pp. 602-611
    • Lloehfeld, M.1    Fahhnan, S.2
  • 7
    • 0024903880 scopus 로고    scopus 로고
    • Design of parallel hardware neural network systems from custom analog VLS1 "building-block" chips
    • June 18-22, 1989 Washington D.C
    • S.P. Eberhardt, T.A. Duong, and A.P. Thakoor, "Design of parallel hardware neural network systems from custom analog VLS1 "building-block" chips," IEEE/INNS Proc. IJCNN, June 18-22, 1989 Washington D.C., vol. 2, pp. 183.
    • IEEE/INNS Proc. IJCNN , vol.2
    • Eberhardt, S.P.1    Duong, T.A.2    Thakoor, A.P.3
  • 10
    • 0000155950 scopus 로고
    • The Cascade Correlation learning architecture
    • Ed: D. Touretzky, Morgan Kaufimann, San Mateo, CA
    • S.E. Fahlmann, C. Lebiere, "The Cascade Correlation learning architecture," in Advances hi Neural hlformation Processing Systems II, Ed: D. Touretzky, Morgan Kaufimann, San Mateo, CA, 1990, pp. 524-532.
    • (1990) Advances Hi Neural Hlformation Processing System , pp. 524-532
    • Fahlmann, S.E.1    Lebiere, C.2
  • 11
    • 0029511861 scopus 로고    scopus 로고
    • Cascade Error Projection-An efficient hardware learning algororithm
    • Western Australia, Oct. 27-Dec I, 1995 (Invited Paper)
    • T.A. Duong, "Cascade Error Projection-An efficient hardware learning algororithm, " Proceeding Int'l IEEE/ICNN in Perth, Western Australia, vol. 1, pp. 175-178, Oct. 27-Dec I, 1995 (Invited Paper)
    • Proceeding Int'l IEEE/ICNN in Perth , vol.1 , pp. 175-178
    • Duong, T.A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.